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preliminary rev 0.6 7/13 copyright ? 2013 by silicon laboratories c8051f85x/86x this information applies to a product under development. its characteristics and specifications are subject to change without n otice. c8051f85x/86x low-cost 8-bit mcu family with up to 8 kb of flash memory - up to 8 kb flash - flash is in-system programmable in 512-byte sectors - up to 512 bytes ram (256 + 256) on-chip debug - on-chip debug circuitry facilitate s full speed, non-intrusive in- system debug (no emulator required) - provides breakpoints, single st epping, inspect/modify memory and registers 12-bit analog-to-digital converter - up to 16 input channels - up to 200 ksps 12-bit mode or 800 ksps 10-bit mode - internal vref or external vref supported internal low-power oscillator - calibrated to 24.5 mhz - low supply current - 2% accuracy over supply and temperature internal low-frequency oscillator - 80 khz nominal operation - low supply current - independent clock source for watchdog timer 2 analog comparators - programmable hysteresis and response time - configurable as interrupt or reset source - low current additional support peripherals - independent watchdog timer clocked from lfo - 16-bit crc engine high-speed cip-51 c core - efficient, pipelined instruction architecture - up to 25 mips throughput with 25 mhz clock - uses standard 8051 instruction set - expanded interrupt handler general-purpose i/o - up to 18 pins - 5 v-tolerant - crossbar-enabled communication peripherals - uart - i 2 c / smbus? - spi? timer/counters and pwm - 4 general-purpose 16-bit timer/counters - 16-bit programmable counter array (pca) with three channels of pwm, capture/compare, or frequency output capability, and hardware kill/safe state capability supply voltage - 2.2 to 3.6 v package options - 16-pin soic - 20-pin qfn, 3 x 3 mm - 24-pin qsop - available in die form - qualified to aec-q100 standards temperature ranges: - C40 to +125 c (-ix) and C40 to +85 c (-gx) cip-51 (25 mhz) 2-8 kb flash 256-512 b ram watchdog supply monitor core / memory / support c2 serial debug / programming core ldo clocking / oscillators 80 khz low frequency oscillator 24.5 mhz low power oscillator external clock (cmos input) clock selection analog peripherals sar adc (12-bit 200 ksps,10-bit 800 ksps) 2 x low current comparators digital peripherals uart 4 x 16-bit timers 3-channel pca voltage reference flexible pin muxing priority crossbar encoder 18 multi-function 5v-tolerant i/o pins i2c / smbus spi 16-bit crc
c8051f85x/86x 2 preliminary rev 0.6 table of contents 1. electrical specifications............... ............................................ ............... .............. ............ ..7 1.1. electrical characteristics ......... ........................................................................... ............7 1.2. typical power curves .... .................................................................................. ............ 17 1.2.1. operating supply curr ent ............... ........................................................... .......... 17 1.2.2. adc supply current ..... ............................................................................. .......... 18 1.3. thermal conditions ........ .................................................................................. ............ 19 1.4. absolute maximum rating s................................................................................ ..........19 2. system overview ............ .................................................................................................. .20 2.1. power ............... ............................................................ ............... ............................ ..... 22 2.1.1. ldo ............... ......................................................................................... .......... 22 2.1.2. voltage supply monito r (vmon0) ............ ................................................. .......... 22 2.1.3. device power modes............. .................................................................. ............ 22 2.2. i/o.................. ......................................................................................... ............. ......... 23 2.2.1. general features....... ................................................................................ ..........23 2.2.2. crossbar ................ .................................................................................. ............ 2 3 2.3. clocking............ ............................................................ ............... ............................ ..... 24 2.4. counters/timers and pwm ............ .................................................................. ............24 2.4.1. programmable counter array (pca0) ............. .......................................... .......... 24 2.4.2. timers (timer 0, timer 1, timer 2 and timer 3).. ............... ......................... ........ 24 2.4.3. watchdog timer (wdt0)......... .................................................................. .......... 24 2.5. communications and other digita l peripherals ............ ............... ......................... ........ 25 2.5.1. universal asynchronous rece iver/transmitter (uart0) ..... ............ ........... ........ 25 2.5.2. serial peripheral interface ( spi0) ............... ............................................... .......... 25 2.5.3. system management bu s / i2c (smbus0) ........ .......................................... ........ 25 2.5.4. 16/32-bit crc (crc0)... ................. ........................................................... .......... 25 2.6. analog peripherals ......... .................................................................................. ............ 26 2.6.1. 12-bit analog-to-digital conv erter (adc0) ............. ................................. ............ 26 2.6.2. low current comparators (c mp0, cmp1) ............. ................................. ............ 26 2.7. reset sources............. .................................................................................. ............... 27 2.8. on-chip debugging........ .................................................................................. ............ 27 3. pin definitions............ .................................................................................................. ...... 28 3.1. c8051f850/1/2/3/4/5 qsop 24 pin definitions ........ .......................................... .......... 28 3.2. c8051f850/1/2/3/4/5 qfn2 0 pin definitions ........... .......................................... .......... 31 3.3. c8051f860/1/2/3/4/5 soic 16 pin definitions.......... .......................................... ..........34 4. ordering information ........ .................................................................................. ............... 37 5. qsop-24 package specifications ...... .................................................................. ............ 39 6. qfn-20 package specifications ....... ...................................................................... .......... 41 7. soic-16 package specificati ons ............... ............................................................. .......... 44 8. memory organization .......... .................................................................................. ............46 8.1. program memory............ .................................................................................. ............ 47 8.1.1. movx instruction and program memory......... .......................................... .......... 47 8.2. data memory........ ............................................................... ............... .............. ............ 47 8.2.1. internal ram.......... .................................................................................. ............47 8.2.2. external ram......... .................................................................................. ............ 48
c8051f85x/86x preliminary rev 0.6 3 8.2.3. special function registers ..... ............... .................................................. ............ 48 9. special function register memory map.............................................................. ............ 49 10. flash memory................ ................................................................................................ ..... 54 10.1.security options........ .................................................................................................. .54 10.2.programming the flash memory .... .................................................................. .......... 56 10.2.1.flash lock and key functions ... ............................................................... ..........56 10.2.2.flash erase procedure.......... .................................................................. ............ 56 10.2.3.flash write procedure......... ...................................................................... .......... 56 10.3.non-volatile data storage.............. .................................................................. ............ 57 10.4.flash write and erase guid elines ............... ........................................................ ........ 57 10.4.1.voltage supply maint enance and the suppl y monitor........ ......................... ........57 10.4.2.pswe maintenance ..... ............................................................................. .......... 57 10.4.3.system clock......... .................................................................................. ............ 58 10.5.flash control registers ............ ......................................................................... .......... 59 11. device identification ....... ................................................................................................ ... 62 11.1.device identification registers. . ......................................................................... .......... 62 12. interrupts .................. ................................................................................................ .......... 65 12.1.mcu interrupt sources and vectors ............ ........................................................ ........65 12.1.1.interrupt priorities .. .................................................................................. ............ 65 12.1.2.interrupt latency........ ................................................................................ .......... 65 12.2.interrupt control registers........ ......................................................................... .......... 67 13. power management and internal re gulator ............. ............................................. .......... 74 13.1.power modes .......... ............................................................ ............... .............. ............ 74 13.1.1.idle mode............... .................................................................................. ............ 74 13.1.2.stop mode ............... .................................................................................. .......... 75 13.2.ldo regulator ............ .................................................................................. ............... 75 13.3.power control registers ........... ......................................................................... .......... 75 13.4.ldo control registers... .................................................................................. ............76 14. analog-to-digital converter (adc0).. ................. .................................................. ............ 78 14.1.adc0 analog mu ltiplexer............... .................................................................. ............ 79 14.2.adc operation............ .................................................................................. ............... 80 14.2.1.starting a conver sion ................................................................................ ..........80 14.2.2.tracking modes ......... ................................................................................ .......... 80 14.2.3.burst mode ....... ......................................................................................... .......... 81 14.2.4.settling time requirements ......... ............................................................. .......... 82 14.2.5.gain setting...... ......................................................................................... .......... 83 14.3.8-bit mode............... .................................................................................. ............... .... 83 14.4.12-bit mode............. .................................................................................................. ... 83 14.5.power considerations.... .................................................................................. ............ 84 14.6.output code formatting .. .................................................................................. .......... 86 14.7.programmable window detector ................... .................................................. ............ 87 14.7.1.window detector in single-e nded mode................ ................................. ............ 87 14.8.voltage and ground reference option s............................................................ .......... 89 14.8.1.external voltage reference... .................................................................. ............ 89 14.8.2.internal voltage refer ence. ................. ........................................................ ........ 89 14.8.3.analog ground reference....... .................................................................. ..........89
c8051f85x/86x 4 preliminary rev 0.6 14.9.temperature sensor ...... .................................................................................. ............ 90 14.9.1.calibration ............. .................................................................................. ............ 90 14.10.adc control registers... .................................................................................. .......... 91 15. cip-51 microcontroller core .......... .......................................... ............... .............. .......... 106 15.1.performance ............... .................................................................................. ............. 1 06 15.2.programming and debugging suppor t ............................... ............... .............. .......... 107 15.3.instruction set ......... .................................................................................................. .107 15.3.1.instruction and cpu timing.... ............... .................................................. .......... 107 15.4.cpu core registers ...... .................................................................................. .......... 112 16. clock sources and selection (h fosc0, lfosc0, and extclk).... ............... ............. 118 16.1.programmable high-freque ncy oscillator............ .............. ............... .............. .......... 118 16.2.programmable low-frequency oscilla tor.................... ................................. ............. 118 16.2.1.calibrating the internal l-f oscillator ......... ................ ............... .............. .......... 118 16.3.external clock.................... ........................................................................... ............. 118 16.4.clock selection ......... .................................................................................. ............... 1 19 16.5.high frequency oscillator control registers........ .............. ............... .............. .......... 120 16.6.low frequency oscillator control registers. ...... ................ ............... .............. .......... 121 16.7.clock selection control register s ................................................................ ............. 122 17. comparators (cmp0 and cmp1)....... ................................................................. ............. 123 17.1.system connectivity ...... .................................................................................. .......... 123 17.2.functional description ... .................................................................................. ..........126 17.3.comparator contro l registers ............ ................................ ............... .............. .......... 127 18. cyclic redundancy check unit (crc0) ............................................................... .......... 133 18.1.crc algorithm ............ .................................................................................. ............. 13 3 18.2.preparing for a crc calc ulation............. ............................ ............... .............. .......... 135 18.3.performing a crc calculation..... ................................................................. ............. 135 18.4.accessing the crc0 result......... ................................................................. ............. 135 18.5.crc0 bit reverse feature ....... .......................................... ............... .............. ..........135 18.6.crc control registers ............. .......................................... ............... .............. .......... 136 19. external interrupts (int0 and int1). ................... .................................................. .......... 142 19.1.external interrupt control registers............. ................................................. ............. 143 20. programmable counter array (pca0) .................................................................. .......... 146 20.1.pca counter/timer. ............................................................ ............... .............. .......... 1 47 20.2.pca0 interrupt so urces ............... ................................................................. ............. 147 20.3.capture/compare modules............ .................................................................. ..........148 20.3.1.output polarity....... .................................................................................. .......... 148 20.3.2.edge-triggered capture mode ............... .................................................. .......... 149 20.3.3.software timer (com pare) mode ................. .............. ............... .............. .......... 150 20.3.4.high-speed output mo de............. .............................. ............... .............. .......... 151 20.3.5.frequency output mode........ .................................................................. .......... 152 20.4.pwm waveform gene ration ................. .............................. ............... .............. .......... 153 20.4.1.edge aligned pwm ........ ............................................ ............... .............. .......... 153 20.4.2.center aligned pwm .... .............................................. ............... .............. .......... 155 20.4.3. 8 to11-bit pulse width modu lator modes............ ................................. ............. 157 20.4.4. 16-bit pulse width modulator mode ................. ............................ ............ ........ 158 20.5.comparator clear function....... .......................................... ............... .............. ..........159
c8051f85x/86x preliminary rev 0.6 5 20.6.pca control registers... .................................................................................. ..........160 21. port i/o (port 0, port 1, port 2, crossbar, and port match) ... ............... .............. .......... 178 21.1.general port i/o initia lization ................ .............................. ............... .............. .......... 179 21.2.assigning port i/o pins to a nalog and digital functions ......... .............. ............ ........ 180 21.2.1.assigning port i/o pins to analog function s.............. ............... .............. ..........180 21.2.2.assigning port i/o pins to digital functions ............... ............... .............. .......... 180 21.2.3.assigning port i/o pins to fixed digital functions ..... ............... .............. .......... 181 21.3.priority crossbar decoder......... .......................................... ............... .............. .......... 182 21.4.port i/o modes of operation ..... .......................................... ............... .............. .......... 184 21.4.1.configuring port pi ns for analog modes ..... .............. ............... .............. .......... 184 21.4.2.configuring port pi ns for digital mode s .................... ............... .............. .......... 184 21.4.3.port drive strength ........... .......................................... ............... .............. .......... 184 21.5.port match.......... ......................................................................................... ............. .. 185 21.6.direct read/write acce ss to port i/o pins..... .................................................. .......... 185 21.7.port i/o and pin confi guration control registers . .............. ............... .............. .......... 186 22. reset sources and supply monitor ... .................................................................. .......... 204 22.1.power-on reset ......... .................................................................................. ............. 2 05 22.2.power-fail reset / supply monito r ............................................................... ............. 206 22.3.enabling the vdd monitor . ................................................. ............... .............. .......... 206 22.4.external reset .......... .................................................................................. ............... 2 07 22.5.missing clock detector re set............................................. ............... .............. .......... 207 22.6.comparator0 reset........ .................................................................................. .......... 207 22.7.watchdog timer reset ...... ................................................. ............... .............. .......... 207 22.8.flash error reset........ .................................................................................. ............. 20 7 22.9.software reset ........... .................................................................................. ............. 20 7 22.10.reset sources control registers. .................................................................. .......... 208 23. serial peripheral interface (spi0) .. .......................................... ............... .............. .......... 214 23.1.signal descriptions ........ .................................................................................. .......... 215 23.1.1.master out, slave in (mosi) ............... ................................................. ............. 215 23.1.2.master in, slave out (miso) .. ............... .................................................. .......... 215 23.1.3.serial clock (sck)..... ................................................. ............... .............. .......... 215 23.1.4.slave select (nss).... ................................................. ............... .............. .......... 2 15 23.2.spi0 master mode operation ... .......................................... ............... .............. .......... 216 23.3.spi0 slave mode operation ..... .......................................... ............... .............. .......... 218 23.4.spi0 interrupt sources .................................................................................. .............218 23.5.serial clock phase and polarity .......................................... ............... .............. ..........218 23.6.spi special function registers ... ................................................................. .............220 23.7.spi control registers .... .................................................................................. .......... 224 24. system management bus / i2c (s mbus0) .............................. ............... .............. .......... 229 24.1.supporting documents . ................... ................................................................ .......... 230 24.2.smbus configuration ..... .................................................................................. .......... 230 24.3.smbus operation.... ............................................................ ............... .............. .......... 230 24.3.1.transmitter vs. receiver...... ................................................................. ............. 231 24.3.2.arbitration ........... .................................................................................. ............. 231 24.3.3.clock low extension . ................................................. ............... .............. .......... 231 24.3.4.scl low timeout ...... ................................................. ............... .............. .......... 231
c8051f85x/86x 6 preliminary rev 0.6 24.3.5.scl high (smbus free) timeout ................. .............. ............... .............. .......... 232 24.4.using the smbus ........... .................................................................................. .......... 232 24.4.1.smbus configuration register .............. .................................................. ..........232 24.4.2.smbus pin swap....... ................................................. ............... .............. ..........234 24.4.3.smbus timing control......... ................................................................. ............. 234 24.4.4.smb0cn control register..... .................................................................. ..........234 24.4.5.hardware slave address rec ognition................. ................................. ............. 236 24.4.6.data register.. ............................................................ ............... .............. .......... 236 24.5.smbus transfer modes ..... ................................................. ............... .............. .......... 237 24.5.1.write sequence (master)......... ................................................................ .......... 237 24.5.2.read sequence (master) . .......................................... ............... .............. .......... 238 24.5.3.write sequence (slave)......... .................................................................. .......... 239 24.5.4.read sequence (slave) ... .......................................... ............... .............. .......... 240 24.6.smbus status decoding .. ................................................................................ .......... 240 24.7.i2c / smbus control registers .... ................................................................. ............. 245 25. timers (timer0, timer1, timer2 and timer3) ....... ............................................... .......... 252 25.1.timer 0 and time r 1.................. .............. ............................ ............... .............. .......... 253 25.1.1.mode 0: 13-bit counter/timer.. ................................................................ .......... 254 25.1.2.mode 1: 16-bit counter/timer.. ................................................................ .......... 254 25.1.3.mode 2: 8-bit counter/timer with auto-reload ............... .............. ............ ........ 255 25.1.4.mode 3: two 8-bit counter/timers (timer 0 only) ........ ............................ ........ 256 25.2.timer 2 and time r 3.................. .......................................... ............... .............. .......... 257 25.2.1.16-bit timer with auto-reload ............... .................................................. .......... 257 25.2.2.8-bit timers with auto-reloa d ................................................................. .......... 258 25.2.3.capture mode.......... ................................................................................ .......... 259 25.3.timer control regi sters ................................................................................ ............. 260 26. universal asynchronous receiver /transmitter (uart0) ............. ........... ............ ........ 278 26.1.enhanced baud rate generation ........... ............................ ............... .............. .......... 278 26.2.operational modes......... .................................................................................. .......... 280 26.2.1.8-bit uart ....... .......................................................... ............... .............. .......... 280 26.2.2.9-bit uart ....... .......................................................... ............... .............. .......... 281 26.3.multiprocessor communications.... .................................................................. .......... 282 26.4.uart control registers ........... .......................................... ............... .............. .......... 2 84 27. watchdog timer (wdt0) ....... ................................................................................ .......... 288 27.1.enabling / resetting the wdt........ .................................................................. .......... 289 27.2.disabling the wdt ...... .................................................................................. ............. 289 27.3.disabling the wdt lockout ................................................ ............... .............. .......... 289 27.4.setting the wdt interval .................................................................................. .......... 289 27.5.watchdog timer control registers. ............... .................................................. .......... 290 28. c2 interface ................ ................................................................................................ ...... 292 28.1.c2 pin sharing.......... .................................................................................. ............... 2 92 28.2.c2 interface registers .................................................................................. .............293 document change list ........ .......................................................... ............... .............. .......... 298 contact information ........... .................................................................................. ............... .. 299
c8051f85x/86x preliminary rev 0.6 7 electrical specifications 1. electrical specifications 1.1. electrical characteristics all electrical parameters in all tables are specified unde r the conditions listed in table 1.1, unless stated otherwise. table 1.1. recommended operating conditions parameter symbol test condition min typ max unit operating supply voltage on vdd v dd 2.2 3.6 v system clock frequency f sysclk 0 25 mhz operating ambient temperature t a commercial grade devices (-gm, -gs, -gu) C40 85 c industrial grade devices (-im, -is, -iu) C40 125 c operating junction temperature t j commercial grade devices (-gm, -gs, -gu) C40 tbd c industrial grade devices (-im, -is, -iu) C40 tbd c note: all voltages with respect to gnd table 1.2. power consumption parameter symbol test condition min typ max unit digital core supply current normal modefull speed with co d e executing from flash i dd f sysclk = 24.5 mhz 2 4.45 tbd ma f sysclk = 1.53 mhz 2 915 tbd ? a f sysclk = 80 khz 3 250 tbd ? a idle modecore halted with pe rip herals running i dd f sysclk = 24.5 mhz 2 2.05 tbd ma f sysclk = 1.53 mhz 2 550 tbd ? a f sysclk = 80 khz 3 125 tbd ? a stop modecore halted and all clocks sto ppe d, supply monitor off. i dd internal ldo on 105 ? a internal ldo off 0.2 ? a notes: 1. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. includ es supply current from internal regulator, supply monitor, and high frequency oscillator 3. includes supply current from internal regulator, supply monitor, and low frequency oscillator 4. adc0 always-on power excludes internal reference supply current 5. the internal reference is enabled as-needed when operating the adc in burst mode to save power.
c8051f85x/86x 8 preliminary rev 0.6 electrical specifications analog peripheral supply currents high-frequency oscillator i hfosc operating at 24.5 mhz, t a = 25 c 155 a low-frequency oscillator i lfosc operating at 80 khz, t a = 25 c 3.5 a adc0 always-on 4 i adc 800 ksps, 10-bit conversions or 200 ksps, 12-bit conversions normal bias settings v dd = 3.0 v 845 tbd a 250 ksps, 10-bit conversions or 62.5 ksps 12-bit conversions low power bias settings v dd = 3.0 v 425 tbd a adc0 burst mode, 10-bit single conve r sions, external reference i adc 200 ksps, v dd = 3.0 v 370 a 100 ksps, v dd = 3.0 v 185 a 10 ksps, v dd = 3.0 v 19 a adc0 burst mode, 10-bit single conve r sions, internal reference, low power bias settings i adc 200 ksps, v dd = 3.0 v 490 a 100 ksps, v dd = 3.0 v 245 a 10 ksps, v dd = 3.0 v 23 a adc0 burst mode, 12-bit single conve r sions, external reference i adc 100 ksps, v dd = 3.0 v 530 a 50 ksps, v dd = 3.0 v 265 a 10 ksps, v dd = 3.0 v 53 a adc0 burst mode, 12-bit single conve r sions, internal reference i adc 100 ksps, v dd = 3.0 v, normal bias 950 a 50 ksps, v dd = 3.0 v, low power bias 420 a 10 ksps, v dd = 3.0 v, low power bias 85 a internal adc0 reference, always- on 5 i iref normal power mode 680 tbd a low power mode 160 tbd a temperature sensor i tsense 75 tbd a table 1.2. power consumption (continued) parameter symbol test condition min typ max unit notes: 1. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. includes supply current from internal regulator, supply monitor, and high frequency oscillator 3. includes supply current from internal regulator, supply monitor, and low frequency oscillator 4. adc0 always-on power excludes internal reference supply current 5. the internal reference is enabled as-needed when operating the adc in burst mode to save power.
c8051f85x/86x preliminary rev 0.6 9 electrical specifications comparator 0 (cmp0), comparator 1 (cmp1) i cmp cpnmd = 11 0.5 a cpnmd = 10 3 a cpnmd = 01 10 a cpnmd = 00 25 a voltage supply monitor (vmon0) i vmon 15 tbd a flash current on vdd write operation i flash-w tbd ma erase operation i flash-e tbd ma table 1.2. power consumption (continued) parameter symbol test condition min typ max unit notes: 1. currents are additive. for example, where i dd is specified and the mode is no t mutually exclusive, enabling the functions increases supply cu rrent by the specified amount. 2. includes supply current from internal regulator, supply monitor, and high frequency oscillator 3. includes supply current from internal regulator, supply monitor, and low frequency oscillator 4. adc0 always-on power excludes internal reference supply current 5. the internal reference is enabled as-needed when operating the adc in burst mode to save power.
c8051f85x/86x 10 preliminary rev 0.6 electrical specifications table 1.3. reset and supply monitor parameter symbol test condition min typ max unit v dd supply monitor threshold v vddm 1.85 1.95 2.1 v power-on reset (por) threshold v por rising voltage on v dd 1.4 v falling voltage on v dd 0.8 1.3 v v dd ramp time t rmp time to v dd > 2.2 v 10 3000 s reset delay from por t por relative to v dd > v por 3 tbd ms reset delay from non-por source t rst time between release of reset source and code execution 30 s rst low time to generate reset t rstl 15 s missing clock detector response t i me (final rising edge to reset) t mcd f sysclk > 1 mhz 0.625 1.2 ms missing clock detector trigger ? frequency f mcd 7.5 13 khz v dd supply monitor turn-on time t mon 2 s table 1.4. flash memory parameter symbol test condition min typ max units write time 1 t write one byte tbd 20 tbd s erase time 1 t erase one page tbd 5 tbd ms v dd voltage during programming 2 v prog 2.2 3.6 v endurance (write/erase cycles) n we 20k 100k cycles notes: 1. does not include sequencing time before and after the writ e/erase ope ration, which may be multiple sysclk cycles. 2. flash can be safely programmed at any voltage above the supply monitor threshold ( v vddm ). 3. da ta retention information is published in the quarterly quality and reliability report.
c8051f85x/86x preliminary rev 0.6 11 electrical specifications table 1.5. internal oscillators parameter symbol test condition min typ max unit high frequency oscillator (24.5 mhz) oscillator frequency f hfosc full temperature and supply range 24 24.5 25 mhz power supply sensitivity pss hfosc t a = 25 c 0.5 %/v temperature sensitivity ts hfosc v dd = 3.0 v 40 ppm/c low frequency oscillator (80 khz) oscillator frequency f lfosc full temperature and supply range 75 80 85 khz power supply sensitivity pss lfosc t a = 25 c 0.05 %/v temperature sensitivity ts lfosc v dd = 3.0 v 65 ppm/c table 1.6. external clock input parameter symbol test condition min typ max unit external input cmos clock frequency (at extclk pin) f cmos 0 25 mhz external input cmos clock high time t cmosh 18 ns external input cmos clock low time t cmosl 18 ns
c8051f85x/86x 12 preliminary rev 0.6 electrical specifications table 1.7. adc parameter symbol test condition min typ max unit resolution n bits 12 bit mode 12 bits 10 bit mode 10 bits throughput rate (high speed mode) f s 12 bit mode 200 ksps 10 bit mode 800 ksps throughput rate (low power mode) f s 12 bit mode 62.5 ksps 10 bit mode 250 ksps tracking time t trk high speed mode 230 ns low power mode 450 ns power-on time t pwr 1.2 s sar clock frequency f sar high speed mode, reference is 2.4 v internal 6.25 mhz high speed mode, reference is not 2.4 v internal 12.5 mhz low power mode 4 mhz conversion time t cnv 10-bit conversion, sar clock = 12.25 mhz, system clock = 24.5 mhz. 1.1 s sample/hold capacitor c sar gain = 1 5 pf gain = 0.5 2.5 pf input pin capacitance c in 20 pf input mux impedance r mux 550 ? voltage reference range v ref 1 v dd v input voltage range* v in gain = 1 0 v ref v gain = 0.5 0 2xv ref v power supply rejection ratio psrr adc 70 db dc performance integral nonlinearity inl 12 bit mode 1 1.9 lsb 10 bit mode 0.2 0.5 lsb differential nonlinearity ? (guaranteed monotonic) dnl 12 bit mode C1 0.7 1.8 lsb 10 bit mode 0.2 0.5 lsb *note: absolute input pin voltage is limited by the v dd supply.
c8051f85x/86x preliminary rev 0.6 13 electrical specifications offset error e off 12 bit mode, vref = 1.65 v C2 0 2 lsb 10 bit mode, vref = 1.65 v C1 0 1 lsb offset temperature coeffi - cient tc off 0.004 lsb/c slope error e m 12 bit mode C0.07 C0.02 0.02 % dynamic performance 10 khz sine wave input 1db below full s cale, max throughput, using agnd pin signal-to-noise snr 12 bit mode tbd 66 db 10 bit mode tbd 60 db signal-to-noise plus distor - tion sndr 12 bit mode tbd 66 db 10 bit mode tbd 60 db total harmonic distortion (up to 5th har m onic) thd 12 bit mode 71 db 10 bit mode 70 db spurious-free dynamic rang e sfdr 12 bit mode C79 db 10 bit mode C74 db table 1.7. adc (continued) parameter symbol test condition min typ max unit *note: absolute input pin voltage is limited by the v dd supply.
c8051f85x/86x 14 preliminary rev 0.6 electrical specifications table 1.8. voltage reference parameter symbol test condition min typ max unit internal fast settling reference output voltage (full temperature and supply ra ng e) v reffs 1.65 v setting 1.62 1.65 1.68 v 2.4 v setting 2.35 2.4 2.45 v temperature coefficient tc reffs 50 ppm/c turn-on time t reffs 1.5 s power supply rejection psrr reffs 400 ppm/v external reference input current i extref sample rate = 800 ksps; vref = 3.0 v 5 a table 1.9. temperature sensor parameter symbol test condition min typ max unit offset v off t a = 0 c 757 mv offset error* e off t a = 0 c tbd mv slope m 2.85 mv/c slope error* e m tbd v/c linearity 0.5 c turn-on time 1.8 s *note: represents one standard deviation from the mean.
c8051f85x/86x preliminary rev 0.6 15 electrical specifications table 1.10. comparators parameter symbol test condition min typ max unit response time, cpnmd = 00 ? (highest speed) t resp0 +100 mv differential 100 ns C100 mv differential 150 ns response time, cpnmd = 11 ? (lowest power) t resp3 +100 mv differential 1.5 s C100 mv differential 3.5 s positive hysterisis mode 0 (cpnmd = 00) hys cp+ cpnhyp = 00 0.4 mv cpnhyp = 01 8 mv cpnhyp = 10 16 mv cpnhyp = 11 32 mv negative hysterisis mode 0 (cpnmd = 00) hys cp- cpnhyn = 00 -0.4 mv cpnhyn = 01 C8 mv cpnhyn = 10 C16 mv cpnhyn = 11 C32 mv positive hysterisis mode 1 (cpnmd = 01) hys cp+ cpnhyp = 00 0.5 mv cpnhyp = 01 6 mv cpnhyp = 10 12 mv cpnhyp = 11 24 mv negative hysterisis mode 1 (cpnmd = 01) hys cp- cpnhyn = 00 -0.5 mv cpnhyn = 01 C6 mv cpnhyn = 10 C12 mv cpnhyn = 11 C24 mv positive hysterisis mode 2 (cpnmd = 10) hys cp+ cpnhyp = 00 0.7 mv cpnhyp = 01 4.5 mv cpnhyp = 10 9 mv cpnhyp = 11 18 mv negative hysterisis mode 2 (cpnmd = 10) hys cp- cpnhyn = 00 -0.6 mv cpnhyn = 01 C4.5 mv cpnhyn = 10 C9 mv cpnhyn = 11 C18 mv
c8051f85x/86x 16 preliminary rev 0.6 electrical specifications positive hysterisis mode 3 (cpnmd = 11) hys cp+ cpnhyp = 00 1.5 mv cpnhyp = 01 4 mv cpnhyp = 10 8 mv cpnhyp = 11 16 mv negative hysterisis mode 3 (cpnmd = 11) hys cp- cpnhyn = 00 -1.5 mv cpnhyn = 01 C4 mv cpnhyn = 10 C8 mv cpnhyn = 11 C16 mv input range (cp+ or cpC) v in -0.25 v dd +0.2 5 v input pin capacitance c cp 7.5 pf common-mode rejection ratio cmrr cp 70 db power supply rejection ratio psrr cp 72 db input offset voltage v off t a = 25 c -10 0 10 mv input offset tempco tc off 3.5 v/c table 1.11. port i/o parameter symbol test condition min typ max unit output high voltage (high drive) v oh i oh = C3 ma v dd C 0.7 v output low voltage (high drive) v ol i ol = 8.5 ma 0.6 v output high voltage (low drive) v oh i oh = C1 ma v dd C 0.7 v output low voltage (low drive) v ol i ol = 1.4 ma 0.6 v input high voltage v ih v dd C 0.6 v input low voltage v il 0.6 v pin capacitance c io 7 pf weak pull-up current (v in = 0 v) i pu v dd = 3.6 C30 C20 C10 a input leakage ? (pullups off or analog) i lk gnd < v in < v dd C1 1 a input leakage current with v in above v dd i lk v dd < v in < v dd +2.0 v 0 5 150 a table 1.10. comparators parameter symbol test condition min typ max unit
c8051f85x/86x preliminary rev 0.6 17 electrical specifications 1.2. typical power curves 1.2.1. operating supply current figure 1.1. typical operating current running from 24.5 mhz internal oscillator figure 1.2. typical operating current running from 80 khz internal oscillator 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 supply current (ma) operating frequency (mhz) normal mode idle mode 100 120 140 160 180 200 220 240 260 10 20 30 40 50 60 70 80 supply current ( a) operating frequency (khz) normal mode idle mode
c8051f85x/86x 18 preliminary rev 0.6 electrical specifications 1.2.2. adc supply current figure 1.3. typical adc and internal reference power consumption in burst mode figure 1.4. typical adc power consumption in normal (always-on) mode 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 20 40 60 80 100 120 supply current ( a) sample rate (ksps) 12rbit burst mode, single conversions internal reference, normal bias internal reference, lp bias other reference 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 50 100 150 200 250 300 supply current ( a) sample rate (ksps) 10r bit burst mode, single conversions internal reference, normal bias internal reference, lp bias other reference 650 700 750 800 850 900 950 100 200 300 400 500 600 700 800 supply current ( a) sample rate (ksps) 10rbit conversions, normal bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v 350 360 370 380 390 400 410 420 430 440 450 50 150 250 supply current ( a) sample rate (ksps) 10rbit conversions, low power bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v 650 700 750 800 850 900 950 25 50 75 100 125 150 175 200 supply current ( a) sample rate (ksps) 12rbit conversions, normal bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v 350 360 370 380 390 400 410 420 430 440 450 10 20 30 40 50 60 supply current ( a) sample rate (ksps) 12rbit conversions, low power bias vdd = 3.6 v vdd = 3.0 v vdd = 2.2 v
c8051f85x/86x preliminary rev 0.6 19 electrical specifications 1.3. thermal conditions 1.4. absolute maximum ratings stresses above those lis ted under table 1.13 may cause permanent damage to the device. this is a stress rating only and functional operation of the de vices at those or any other conditions above those indicated in the operation listings of this specification is not im plied. exposure to maximum rating condit ions for extended periods may affect device reliability. table 1.12. thermal conditions parameter symbol test condition min typ max unit thermal resistance* ? ja soic-16 packages tbd c/w qfn-20 packages tbd c/w qsop-24 packages tbd c/w *note: thermal resistance assumes a multi-layer pcb with any exposed pad soldered to a pcb pad. table 1.13. absolute maximum ratings parameter symbol test condition min typ max ambient temperature under bias t bias C55 125 c storage temperature t stg C65 150 c voltage on vdd v dd gndC0.3 4.2 v voltage on i/o pins or rst v in v dd > 3.3 v gndC0.3 5.8 v v dd < 3.3 v gndC0.3 v dd +2.5 v total current sunk into supply pin i vdd 400 ma total current sourced out of ground pin i gnd 400 ma current sourced or sunk by any i/o pin or rst i pio -100 100 ma power dissipation at t a = 125 c p d soic-16 packages tbd mw qfn-20 packages tbd mw qsop-24 packages tbd mw
c8051f85x/86x 20 preliminary rev 0.6 system overview 2. system overview the c8051f85x/86x device family are fully integrated, mi xed-signal system-on-a-chip mcus. highlighted features are listed below. refer to table 4.1 for specific product feature selection and part ordering numbers. ?? core: ?? pipelined cip-51 core ?? fully compatible with standard 8051 instruction set ?? 70% of instructions execute in 1-2 clock cycles ?? 25 mhz maximum operating frequency ?? memory: ?? 2-8 kb flash; in-system progra mmable in 512-byte sectors ?? 512 bytes ram (including 256 bytes standard 8051 ram and 256 bytes on-chip xram) ?? power: ?? internal low drop-out (ldo) regulator for cpu core voltage ?? power-on reset circuit and brownout detectors ?? i/o: up to 18 total multifunction i/o pins: ?? all pins 5 v tolerant under bias ?? flexible peripheral crossbar for peripheral routing ?? 5 ma source, 12.5 ma sink allows direct drive of leds ?? clock sources: ?? low-power internal oscillator: 24.5 mhz 2% ?? low-frequency internal oscillator: 80 khz ?? external cmos clock option ?? timers/counters and pwm: ?? 3-channel programmable counter array (pca) supporti ng pwm, capture/compare and frequency output modes ?? 4x 16-bit general-purpose timers ?? independent watchdog timer, clocked from low frequency oscillator ?? communications and other digital peripherals: ?? uart ?? spi ? ?? i 2 c / smbus ? ?? 16-bit crc unit, supporting automatic crc of flash at 256-byte boundaries ?? analog: ?? 12-bit analog-to-digital converter (adc) ?? 2 x low-current comparators ?? on-chip debugging with on-chip power-on reset, volta ge s upply monitor, watchdog timer, and clock oscillator, the c8051f85x/86x devices are truly standalone system-on-a-chip solutions. the flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field upgrades of the firmware. the on-chip debugging interface (c2) allows non-intrus ive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging. each device is specified for 2.2 to 3.6 v operation, and are available in 20-pin qfn, 16-pin soic or 24-pin qsop packages. all package options are lead-free and rohs co mpliant. the device is available in two temperature grades: -40 to +85 c or C40 to +125 c. see table 4.1 fo r ordering information. a block diagram is included in figure 2.1.
c8051f85x/86x preliminary rev 0.6 21 system overview figure 2.1. c8051f85x/86x family block diagram (qsop-24 shown) port 0 drivers digital peripherals priority crossbar decoder p0.0/vref p0.1/agnd p0.2 p0.3/extclk p0.4/tx p0.5/rx p0.6/cnvstr p0.7 crossbar control port i/o configuration cip-51 8051 controller core 8k byte isp flash program memory 256 byte sram sfr bus 256 byte xram port 2 driver p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 crc analog peripherals 2 comparators power net vdd gnd sysclk system clock configuration cmos oscillator input 24.5 mhz 2% oscillator debug / programming hardware power on reset reset c2d c2ck/rst 12/10 bit adc a m u x temp sensor vref vdd vdd extclk low-freq. oscillator independent watchdog timer internal reference + - + - port 1 drivers p2.0/c2d p1.6 p1.7 p2.1 uart timers 0, 1, 2, 3 3-ch pca i2c / smbus spi
c8051f85x/86x 22 preliminary rev 0.6 system overview 2.1. power 2.1.1. ldo the c8051f85x/86x devices include an internal regulator to regulate the supply voltage down the core operating volta ge of 1.8 v. this ldo consumes little power, but can be shut down in the power-saving stop mode. 2.1.2. voltage supply monitor (vmon0) the c8051f85x/86x devices include a voltage supply monito r wh ich allows devices to function in known, safe operating condition without the need for external hardware. the supply monitor module includes the following features: ?? holds the device in reset if the main v dd supply drops below the vdd reset threshold. 2.1.3. device power modes the c8051f85x/86x devices feature th ree low powe r modes in addition to normal operating mode, allowing the designer to save power when the core is not in use. all power modes are detailed in table 2.1. in addition, the user may choose to lower the clock speed in normal and idle modes to save power when the cpu requirement s allow for lower speed. table 2.1. c8051f85x/86x power modes mode description mode entrance mode exit normal core and peripherals operating at full speed idle ?? core halted ?? peripherals operate at full speed set idle bit in pcon an y e nabled interrupt or reset source stop ?? all clocks stopped ?? core ldo and (optionally) comparators still running ?? pins retain state clear stopcf in reg0md an d se t stop bit in pcon device reset shutdown ?? all clocks stopped ?? core ldo and all analog circuits shut down ?? pins retain state set stopcf in reg0md an d se t stop bit in pcon device reset
c8051f85x/86x preliminary rev 0.6 23 system overview 2.1.3.1. normal mode normal mode encompasses the typical fu ll-speed operation. the power consumpt ion of the device in this mode will vary depending on the system clock speed and any analog peripherals that are enabled. 2.1.3.2. idle mode setting the idle bit in pcon causes the hardware to hal t the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal regist ers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle bit to be cleared and the cpu to resume operation. the pending interrupt will be serviced and the next instruction to be executed after the retu rn from interrupt (reti) will be the instruction immediately following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. 2.1.3.3. stop mode (regulator on) setting the stop bit in pcon when stopcf in reg0cn is clear causes the controller core to enter stop mode as soon as the instruction that sets the bit completes execution. in stop mode the internal oscillator, cpu, and all digital peripherals are stopped. each analog peripheral ma y be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. 2.1.3.4. shutdown mode (regulator off) shutdown mode is an extension of the normal stop mode operation. setting the stop bit in pcon when stopcf in reg0cn is also set causes the controller core to enter shutdown mode as soon as the instruction that sets the bit completes execution, and then the internal regulator is powered down. in shutdown mode, all core functions, memories and peripherals are powered off. an external pin reset or power-on reset is required to exit shutdown mode. 2.2. i/o 2.2.1. general features the c8051f85x/86x ports have the following features: ?? push-pull or open-drain output modes and analog or digital modes. ?? port match allows the device to recognize a change on a port pin value and wake from idle mode or generate an interrupt. ?? internal pull-up resistors can be globally enabled or disabled. ?? two external interrupts provide unique interrup t vectors for monitoring time-critical events. ?? above-rail tolerance allows 5 v interface when device is powered. 2.2.2. crossbar the c8051f85x/86x devices have a digital peri ph eral crossbar with the following features: ?? flexible peripheral assignment to port pins. ?? pins can be individually skipped to move peripherals as needed for design or layout considerations. the crossbar has a fixed priority for each i/o function and assign s these functions to the port pins. when a digital resource is selected, the least-significant unassigned port pi n is assigned to that resource. if a port pin is assigned, the crossbar skips that pin wh en assigning the next select ed resource. additionally, th e crossbar will skip port pins whose associated bits in the pnskip regi sters are set. this provides some flexibility when designing a system: pins involved with sensitive analog measurements can be move d away from digital i/o and peripherals can be moved around the chip as needed to ease layout constraints.
c8051f85x/86x 24 preliminary rev 0.6 system overview 2.3. clocking the c8051f85x/86x devices have two inte rnal oscillators and the option to use an external cmos input at a pin as the system clock. a programmable divider allows the user to internally run the system clock at a slower rate than the selected oscillator if desired. 2.4. counters/timers and pwm 2.4.1. programmable counter array (pca0) the c8051f85x/86x devices include a three-channel, 16 -bit programmable counter array with the following features: ?? 16-bit time base. ?? programmable clock divisor and clock source selection. ?? three independently-configurable channels. ?? 8, 9, 10, 11 and 16-bit pwm modes (center or edge-aligned operation). ?? output polarity control. ?? frequency output mode. ?? capture on rising, falling or any edge. ?? compare function for arbitrary waveform generation. ?? software timer (internal compare) mode. ?? can accept hardware kill si gnal from comparator 0. 2.4.2. timers (timer 0, timer 1, timer 2 and timer 3) timers include the following features: ?? timer 0 and timer 1 are standard 8051 timers, supp orting backwards-compati bility with firmware and hardware. ?? timer 2 and timer 3 can each operate as 16-bit auto-reload or two independent 8-bit auto-reload timers, and include pin or lfo cl ock capture capabilities. 2.4.3. watchdog timer (wdt0) the watchdog timer includes a 16-bit timer with a progr a mmable reset period. the registers are protected from inadvertent access by an independent lock and key interface. the watchdog timer has the following features: ?? programmable timeout interval. ?? runs from the low frequency oscillator. ?? lock-out feature to prevent any modification until a system reset.
c8051f85x/86x preliminary rev 0.6 25 system overview 2.5. communications and other digital peripherals 2.5.1. universal asynchronous receiver/transmitter (uart0) the uart uses two signals (tx and rx) and a predet ermine d fixed baud rate to provide asynchronous communications with other devices. the uart module provides the following features: ?? asynchronous transmissions and receptions. ?? baud rates up to sysclk / 2 (tra nsmit) or sysclk / 8 (receive). ?? 8 or 9 bit data. ?? automatic start and stop generation. 2.5.2. serial peripheral interface (spi0) spi is a 3- or 4-wire communication in terface that includes a clock, input da ta, output data, and an optional select signal. the spi module includes the following features: ?? supports 3- or 4-wire master or slave modes. ?? supports external clock frequencies up to sysclk / 2 in master mode and sysclk / 10 in slave mode. ?? support for all clock phase and polarity modes. ?? 8-bit programmable clock rate. ?? support for multiple masters on the same data lines. 2.5.3. system management bus / i2c (smbus0) the smbus interface is a two-wire, bi-directional serial bus com patible with both i2c and smbus protocols. the two clock and data signals operate in open-drain mode wit h external pull-ups to support automatic bus arbitration. reads and writes to the interface are byte oriented with the sm bus interface autonomously controlling the serial transfer of the data. data can be transferred at up to 1/ 8th of the system clock as a master or slave, which can be faster than allowed by the smbus / i2 c specification, dep ending on the clock source used. a method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple masters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and generation. the smbus module includes the following features: ?? standard (up to 100 kbps) and fast (400 kbps) transfer speeds. ?? support for master, slave, and multi-master modes. ?? hardware synchronization and arbitration for multi-master mode. ?? clock low extending (clock stretching) to interface with faster masters. ?? hardware support for 7-bit slave and general call address recognition. ?? firmware support for 10-bit slave address decoding. ?? ability to inhibit all slave states. ?? programmable data setup/hold times. 2.5.4. 16/32-bit crc (crc0) the crc module is designed to provide hardware calculat ions for fla sh memory verification and communications protocols. the crc module supports the standard ccitt-16 16-bit polynomial (0x1021), and includes the following features: ?? support for four ccitt-16 polynomial. ?? byte-level bit reversal. ?? automatic crc of flash contents on one or more 256-byte blocks. ?? initial seed selection of 0x0000 or 0xffff.
c8051f85x/86x 26 preliminary rev 0.6 system overview 2.6. analog peripherals 2.6.1. 12-bit analog-to-digital converter (adc0) the adc0 module on c8051f85x/86x devices is a success ive approximation register (sar) analog to digit al converter (adc). the key features of the adc module are: ?? single-ended 12-bit and 10-bit modes. ?? supports an output update rate of 200 ksps samples per second in 12-b it mode or 800 ksps samples per second in 10-bit mode. ?? operation in low power modes at lower conversion speeds. ?? selectable asynchronous hardware conversion trigger ?? output data window comparator allows automatic range checking. ?? support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time. ?? conversion complete and window compare interrupts supported. ?? flexible output data formatting. ?? includes an internal fast-settling reference with two levels (1.65 v and 2.4 v) and support for external re ference and signal ground. 2.6.2. low current comparators (cmp0, cmp1) the comparators take two analog input voltages and output the r e lationship between these voltages (less than or greater than) as a digital signal. the low power comparator module includes the following features: ?? multiple sources for the positive and negativ e poles, including vdd, vref, and i/o pins. ?? two outputs are available: a digital synchronous la tched output and a digita l asynchronous raw output. ?? programmable hysteresis and response time. ?? falling or rising edge interrupt opt ions on the co mparator output. ?? provide kill signal to pca module. ?? comparator 0 can be used to reset the device.
c8051f85x/86x preliminary rev 0.6 27 system overview 2.7. reset sources reset circuitry allows the cont roller to be easily placed in a predefined default condition. on entry to this reset state, the following occur: ?? the core halts program execution. ?? module registers are initialized to their defined reset values unless the bits reset only with a power-on reset. ?? external port pins are forced to a known state. ?? interrupts and timers are disabled. all registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. the contents of ram are unaffected during a reset; any previously stored data is preserved as long as power is not lost. the port i/o latches are reset to 1 in open-drain mode. weak pullups are enabled during and after the reset. for vdd supply monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the internal low- power oscillator. the watchdog timer is enabled with th e low frequency oscillator (l fo0) as its clock source. program execution begins at location 0x0000. 2.8. on-chip debugging the c8051f85x/86x devices in clude an on-chip silicon labs 2-wire (c2) debug interfac e to allow flash program- ming and in-system debugging with the production part installed in the end application. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interface specification for details on the c2 protocol.
c8051f85x/86x 28 preliminary rev 0.6 pin definitions 3. pin definitions 3.1. c8051f850/1/2/3/4/ 5 qsop24 pin definitions figure 3.1. c8051f851/2/3/4/5/6-gu and c8051f851/2/3/4/5/6-iu pinout table 3.1. pin definitions for c8051f851/2/3/4/5/6-gu and c8051f851/2/3/4/5/6-iu pin name type pin numbers crossbar capability additional digital functions analog functions gnd ground 5 vdd power 6 rst / c2ck active-low reset / c2 debug clock 7 p0.0 standard i/o 4 yes p0mat.0 int0.0 int1.0 adc0.0 cp0p.0 cp0n.0 vref n/c p0.2 p0.1 / agnd p0.0 / vref gnd vdd rst / c2ck c2d / p2.0 p1.7 p1.6 p1.5 p2.1 n/c p0.3 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 n/c 2 1 4 3 5 6 7 24 pin qsop (top view) 8 9 10 11 12 23 24 21 22 20 19 18 17 16 15 14 13
c8051f85x/86x preliminary rev 0.6 29 pin definitions p0.1 standard i/o 3 yes p0mat.1 int0.1 int1.1 adc0.1 cp0p.1 cp0n.1 agnd p0.2 standard i/o 2 yes p0mat.2 int0.2 int1.2 adc0.2 cp0p.2 cp0n.2 p0.3 / extclk standard i/o / external cmos clock input 23 yes p0mat.3 extclk int0.3 int1.3 adc0.3 cp0p.3 cp0n.3 p0.4 standard i/o 22 yes p0mat.4 int0.4 int1.4 adc0.4 cp0p.4 cp0n.4 p0.5 standard i/o 21 yes p0mat.5 int0.5 int1.5 adc0.5 cp0p.5 cp0n.5 p0.6 standard i/o 20 yes p0mat.6 cnvstr int0.6 int1.6 adc0.6 cp0p.6 cp0n.6 p0.7 standard i/o 19 yes p0mat.7 int0.7 int1.7 adc0.7 cp0p.7 cp0n.7 p1.0 standard i/o 18 yes p1mat.0 adc0.8 cp1p.0 cp1n.0 p1.1 standard i/o 17 yes p1mat.1 adc0.9 cp1p.1 cp1n.1 table 3.1. pin definitions for c8051f851/2/3/4/5/6-gu and c8051f851/2/3/4/5/6-iu pin name type pin numbers crossbar capability additional digital functions analog functions
c8051f85x/86x 30 preliminary rev 0.6 pin definitions p1.2 standard i/o 16 yes p1mat.2 adc0.10 cp1p.2 cp1n.2 p1.3 standard i/o 15 yes p1mat.3 adc0.11 cp1p.3 cp1n.3 p1.4 standard i/o 14 yes p1mat.4 adc0.12 cp1p.4 cp1n.4 p1.5 standard i/o 11 yes p1mat.5 adc0.13 cp1p.5 cp1n.5 p1.6 standard i/o 10 yes p1mat.6 adc0.14 cp1p.6 cp1n.6 p1.7 standard i/o 9 yes adc0.15 cp1p.7 cp1n.7 p2.0 / c2d standard i/o / c2 debug data 8 p2.1 standard i/o 12 n/c no connection 1 13 24 table 3.1. pin definitions for c8051f851/2/3/4/5/6-gu and c8051f851/2/3/4/5/6-iu pin name type pin numbers crossbar capability additional digital functions analog functions
c8051f85x/86x preliminary rev 0.6 31 pin definitions 3.2. c8051f850/1/2/3/4/ 5 qfn20 pin definitions figure 3.2. c8051f851/2/3/4/5/6-gm and c8051f851/2/3/4/5/6-im pinout table 3.2. pin definitions for c8051f851/2/3/4/5/6-gm and c8051f851/2/3/4/5/6-im pin name type pin numbers crossbar capability additional digital functions analog functions gnd ground center 3 12 vdd power 4 rst / c2ck active-low reset / c2 debug clock 5 20 19 18 17 2 3 4 5 7 8 9 10 15 14 13 12 20 pin qfn (top view) p0.1 / agnd p0.0 / vref gnd vdd rst / c2ck c2d / p2.0 p1.6 p1.5 p1.4 p1.3 p0.6 p0.7 p1.0 p1.1 gnd p1.2 p0.2 p0.3 p0.4 p0.5 gnd 1 6 11 16
c8051f85x/86x 32 preliminary rev 0.6 pin definitions p0.0 standard i/o 2 yes p0mat.0 int0.0 int1.0 adc0.0 cp0p.0 cp0n.0 vref p0.1 standard i/o 1 yes p0mat.1 int0.1 int1.1 adc0.1 cp0p.1 cp0n.1 agnd p0.2 standard i/o 20 yes p0mat.2 int0.2 int1.2 adc0.2 cp0p.2 cp0n.2 p0.3 standard i/o 19 yes p0mat.3 extclk int0.3 int1.3 adc0.3 cp0p.3 cp0n.3 p0.4 standard i/o 18 yes p0mat.4 int0.4 int1.4 adc0.4 cp0p.4 cp0n.4 p0.5 standard i/o 17 yes p0mat.5 int0.5 int1.5 adc0.5 cp0p.5 cp0n.5 p0.6 standard i/o 16 yes p0mat.6 cnvstr int0.6 int1.6 adc0.6 cp0p.6 cp0n.6 p0.7 standard i/o 15 yes p0mat.7 int0.7 int1.7 adc0.7 cp0p.7 cp0n.7 table 3.2. pin definitions for c8051f851/2/3/4/5/6-gm and c8051f851/2/3/4/5/6-im pin name type pin numbers crossbar capability additional digital functions analog functions
c8051f85x/86x preliminary rev 0.6 33 pin definitions p1.0 standard i/o 14 yes p1mat.0 adc0.8 cp1p.0 cp1n.0 p1.1 standard i/o 13 yes p1mat.1 adc0.9 cp1p.1 cp1n.1 p1.2 standard i/o 11 yes p1mat.2 adc0.10 cp1p.2 cp1n.2 p1.3 standard i/o 10 yes p1mat.3 adc0.11 cp1p.3 cp1n.3 p1.4 standard i/o 9 yes p1mat.4 adc0.12 cp1p.4 cp1n.4 p1.5 standard i/o 8 yes p1mat.5 adc0.13 cp1p.5 cp1n.5 p1.6 standard i/o 7 yes p1mat.6 adc0.14 cp1p.6 cp1n.6 p2.0 / c2d standard i/o / c2 debug data 6 table 3.2. pin definitions for c8051f851/2/3/4/5/6-gm and c8051f851/2/3/4/5/6-im pin name type pin numbers crossbar capability additional digital functions analog functions
c8051f85x/86x 34 preliminary rev 0.6 pin definitions 3.3. c8051f860/1/2/3/4/ 5 soic16 pin definitions figure 3.3. c8051f861/2/3/4/5/6-gs and c8051f861/2/3/4/5/6-is pinout table 3.3. pin definitions for c8051f861/2/3/4/5/6-gs and c8051f861/2/3/4/5/6-is pin name type pin numbers crossbar capability additional digital functions analog functions gnd ground 4 vdd power 5 rst / c2ck active-low reset / c2 debug clock 6 p0.0 standard i/o 3 yes p0mat.0 int0.0 int1.0 adc0.0 cp0p.0 cp0n.0 p0.1 standard i/o 2 yes p0mat.1 int0.1 int1.1 adc0.1 cp0p.1 cp0n.1 p0.2 p0.1 / agnd p0.0 / vref gnd vdd rst / c2ck c2d / p2.0 p1.3 p0.3 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 2 1 4 3 5 6 7 15 16 13 14 12 11 10 16 pin soic (top view) 8 9
c8051f85x/86x preliminary rev 0.6 35 pin definitions p0.2 standard i/o 1 yes p0mat.2 int0.2 int1.2 adc0.2 cp0p.2 cp0n.2 p0.3 / extclk standard i/o / external cmos clock input 16 yes p0mat.3 extclk int0.3 int1.3 adc0.3 cp0p.3 cp0n.3 p0.4 standard i/o 15 yes p0mat.4 int0.4 int1.4 adc0.4 cp0p.4 cp0n.4 p0.5 standard i/o 14 yes p0mat.5 int0.5 int1.5 adc0.5 cp0p.5 cp0n.5 p0.6 standard i/o 13 yes p0mat.6 cnvstr int0.6 int1.6 adc0.6 cp1p.0 cp1n.0 p0.7 standard i/o 12 yes p0mat.7 int0.7 int1.7 adc0.7 cp1p.1 cp1n.1 p1.0 standard i/o 11 yes p1mat.0 adc0.8 cp1p.2 cp1n.2 p1.1 standard i/o 10 yes p1mat.1 adc0.9 cp1p.3 cp1n.3 p1.2 standard i/o 9 yes p1mat.2 adc0.10 cp1p.4 cp1n.4 table 3.3. pin definitions for c8051f861/2/3/4/5/6-gs and c8051f861/2/3/4/5/6-is pin name type pin numbers crossbar capability additional digital functions analog functions
c8051f85x/86x 36 preliminary rev 0.6 pin definitions p1.3 standard i/o 8 yes p1mat.3 adc0.11 cp1p.5 cp1n.5 p2.0 / c2d standard i/o / c2 debug data 7 table 3.3. pin definitions for c8051f861/2/3/4/5/6-gs and c8051f861/2/3/4/5/6-is pin name type pin numbers crossbar capability additional digital functions analog functions
c8051f85x/86x preliminary rev 0.6 37 ordering information 4. ordering information figure 4.1. c8051f85x/86x part numbering all c8051f85x/86x family member s have the following features: ?? cip-51 core running up to 25 mhz ?? two internal oscillators (24.5 mhz and 80 khz) ?? i2c/smbus ?? spi ?? uart ?? 3-channel programmable counter array (pwm, clock generation, capture/compare) ?? 4 16-bit timers ?? 2 analog comparators ?? 16-bit crc unit in addition to these features, each part number in the c8 0 5 1f85x/86x family has a set of features that vary across the product line. the product selection guide in table 4. 1 shows the features available on each family member. c8051 f 850 C b C silicon labs 8051 family memory type C f (flash) family and features C 85x and 86x revision temperature grade g (-40 to +85), i (-40 to +125) g m package type m (qfn), u (qsop), s (ssop)
c8051f85x/86x 38 preliminary rev 0.6 ordering information table 4.1. product selection guide ordering part number flash memory (kb) ram (bytes) digital port i/os (total) number of adc0 channels i/o with comparator 0/1 inputs pb-free (rohs compliant) aec-q100 qualified temperature range package C8051F850-B-GM 8 512 16 15 15 ? ? -40 to 85 c qfn-20 c8051f850-b-gu 8 512 18 16 16 ? ? -40 to 85 c qsop-24 c8051f851-b-gm 4 512 16 15 15 ? ? -40 to 85 c qfn-20 c8051f851-b-gu 4 512 18 16 16 ? ? -40 to 85 c qsop-24 c8051f852-b-gm 2 256 16 15 15 ? ? -40 to 85 c qfn-20 c8051f852-b-gu 2 256 18 16 16 ? ? -40 to 85 c qsop-24 c8051f853-b-gm 8 512 16 15 ? ? -40 to 85 c qfn-20 c8051f853-b-gu 8 512 18 16 ? ? -40 to 85 c qsop-24 c8051f854-b-gm 4 512 16 15 ? ? -40 to 85 c qfn-20 c8051f854-b-gu 4 512 18 16 ? ? -40 to 85 c qsop-24 c8051f855-b-gm 2 256 16 15 ? ? -40 to 85 c qfn-20 c8051f855-b-gu 2 256 18 16 ? ? -40 to 85 c qsop-24 c8051f860-b-gs 8 512 13 12 12 ? ? -40 to 85 c soic-16 c8051f861-b-gs 4 512 13 12 12 ? ? -40 to 85 c soic-16 c8051f862-b-gs 2 256 13 12 12 ? ? -40 to 85 c soic-16 c8051f863-b-gs 8 512 13 12 ? ? -40 to 85 c soic-16 c8051f864-b-gs 4 512 13 12 ? ? -40 to 85 c soic-16 c8051f865-b-gs 2 256 13 12 ? ? -40 to 85 c soic-16 -im, -iu and -is extended temperature range devices (-40 to 125 c) availa ble in q4 2013.
c8051f85x/86x preliminary rev 0.6 39 qsop-24 package specifications 5. qsop-24 package specifications figure 5.1. qsop-24 package drawing table 5.1. qsop-24 package dimensions dimension min nom max dimension min nom max a 1.75 e 0.635 bsc a1 0.10 0.25 l 0.40 1.27 b 0.20 0.30 ? 0o 8o c 0.10 0.25 aaa 0.20 d 8.65 bsc bbb 0.18 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.10 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. t his drawing conforms to je dec outlin e mo-137, variation ae. 4. recommended card reflow profile is per the je d ec/ipc j-std-020 specification for small body components.
c8051f85x/86x 40 preliminary rev 0.6 qsop-24 package specifications figure 5.2. qsop-24 pcb land pattern table 5.2. qsop-24 pcb land pattern dimensions dimension min max c 5.20 5.30 e 0 .635 bsc x 0.30 0.40 y 1.50 1.60 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. so lder mask design 3. all metal pads are to be non-solder ma sk de fined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a st ainless steel, laser-cut and electro-po lished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thicknes s sh ould be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size shou ld be 1:1 for all perimeter pads. card assembly 7. a no-cle an, t ype-3 solder paste is recommended. 8. the recommended card reflow profile is per the jedec/ipc j-std-020 spe cification for small body components. ?
c8051f85x/86x preliminary rev 0.6 41 qfn-20 package specifications 6. qfn-20 package specifications figure 6.1. qfn-20 package drawing table 6.1. qfn-20 package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.70 0.75 0.80 f 2.53 bsc a1 0.00 0.02 0.05 l 0.3 0.40 0.5 b 0.20 0.25 0.30 l1 0.00 0.10 c 0.27 0.32 0.37 aaa 0.05 d 3.00 bsc bbb 0.05 d2 1.6 1.70 1.8 ccc 0.08 e 0.50 bsc ddd 0.10 e 3.00 bsc eee 0.10 e2 1.6 1.70 1.8 notes: 1. all dime nsion s are shown in millimeters unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
c8051f85x/86x 42 preliminary rev 0.6 qfn-20 package specifications figure 6.2. qfn-20 landing diagram
c8051f85x/86x preliminary rev 0.6 43 qfn-20 package specifications table 6.2. qfn-20 landing diagram dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 d2 1.60 1.80 w 0.34 e 0.50 bsc x 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze 3.31 f 2.53 bsc zd 3.31 gd 2.10 notes: general 1. all dimens ions shown are in millimeters (mm) unless otherwise noted. 2. dimensi onin g and tolerancing is per the ansi y14.5m- 1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimens ions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. ? notes: solder mask design 1. all met al pads are to be non-solder mask defined (nsmd). clearance between the solde r mask and the metal pad is to be 60 m minimum, all the way around the pad. ? notes: stencil design 1. a st ainless steel, laser-cut and electro-po lishe d stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides appro ximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. ? notes: card assembly 1. a no -clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is pe r th e jedec/ipc j-std-020 specification for small body components.
c8051f85x/86x 44 preliminary rev 0.6 soic-16 package specifications 7. soic-16 package specifications figure 7.1. soic-16 package drawing table 7.1. soic-16 package dimensions dimension min nom max dimension min nom max a 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc a2 1.25 h 0.25 0.50 b 0.31 0.51 ? 0o 8o c 0.17 0.25 aaa 0.10 d 9.90 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. t his drawing conforms to the jedec so lid state outline ms-012, variation ac. 4. recommended card reflow profile is per the je d ec/ipc j-std-020 specification for small body components.
c8051f85x/86x preliminary rev 0.6 45 soic-16 packag e specifications figure 7.2. soic-16 pcb land pattern table 7.2. soic-16 pcb land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on ipc-7 351 p attern soic127p600x165-16n for density level b (median land protrusion). 3. all feature sizes shown are at maximum materi al condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
c8051f85x/86x 46 preliminary rev 0.6 memory organization 8. memory organization the memory organization of the cip-51 system controlle r is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f85x/86x device family is shown in figure 8.1. figure 8.1. c8051f85x/86x memory map (8 kb flash version shown) program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function registers (direct addressing only) data memory (ram) 32 general purpose registers 0x1f 0x20 0x2f 32 bit-addressable bytes lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 256 bytes (accessable using movx instruction) 0x0000 0x00ff same 256 bytes as 0x0000 to 0x00ff, wrapped on 256-byte boundaries 0x0100 0xffff 8 kb flash (in-system programmable in 512 byte sectors) 0x0000 0x1fff
c8051f85x/86x preliminary rev 0.6 47 memory organization 8.1. program memory the cip-51 core has a 64 kb program memory space. the c8051f85x/86x family implements 8 kb, 4 kb or 2 kb of this program memory space as in -system, re-programmable flash memory. the last address in the flash block (0x1fff on 8 kb devices, 0x0fff on 4 kb devices and 0x07 ff on 2 kb devices) serves as a security lock byte for the device, and provides read, write a nd erase protection. addresses above the lock byte within the 64 kb address space are reserved. figure 8.2. flash program memory map 8.1.1. movx instruction and program memory the movx instruction in an 8051 device is typically used to access external data memory. on the c8051f85x/86x devices, the movx instruction is normally used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash memory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase and write flash. this flash access feature provides a mechanism for the c8051f85x/86x to update program code and use the progra m memory space for non-volatile data storage. refer to section 10. flash memory on page 54 for further details. 8.2. data memory the c8051f85x/86x device family includes up to 512 by tes of ram data memory. 256 bytes of this memory is mapped into the internal ram space of the 8051. on devi ces with 512 bytes total ram, 256 additional bytes of memory are available as on-chip external memory. the data memory map is shown in figure 8.1 for reference. 8.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 1 28 bytes of data memory are used for general purpose regi sters and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 byte s of data memory. locations 0x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisti ng of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function registers (sfr) bu t is physically separate from the sfr space. the addressing mode used by an instruction when accessin g locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data me mory space or the sfrs. instructi ons that use direct addressing will access the sfr space. instructions using indirect add ressing above 0x7f access the upper 128 bytes of data memory. figure 8.1 illustrates the data memo ry organization of the c8051f85x/86x. lock byte 0x0000 0x07ff 0x07fe flash memory organized in 512-byte pages 0x0600 flash memory space lock byte 0x0000 0x0fff 0x0ffe 0x0e00 flash memory space lock byte 0x0000 0x1fff 0x1ffe 0x1e00 flash memory space c8051f850/3 c8051f860/3 c8051f851/4 c8051f861/4 c8051f852/5 c8051f862/5 lock byte page lock byte page lock byte page
c8051f85x/86x 48 preliminary rev 0.6 memory organization 8.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 thro ugh 0x1f, may be addressed as four banks of general- purpose registers. each bank consists of eight byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bits in the progra m status word (psw) register, rs0 and rs1, select the active register bank. this allows fa st context switching when entering subr outines and interrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 8.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individu ally addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the by te at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). the mcs-51? assembly language allows an alternate notati on for bit addressing of the form xx.b where xx is the byte address and b is the bit position with in the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 8.2.1.3. stack a programmer's stack can be located anywhere in the 256 -byte data memory. the stack area is designated using the stack pointer (sp) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp+1 and then sp is incremented. a reset initia lizes the stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, wh ich is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 8.2.2. external ram on devices with 512 bytes total ram, there are 256 bytes of on-chip ram mapped into the external data memory space. all o f these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. no te: the 16-bit movx instruction is also used for writes to the flash memory. see section 10. flash memory on page 54 for details. the movx instruction accesses xram by default. for a 16-bit movx operation (@dptr), the upper 8 bits of the 16-bit external data memory address word are "don't cares". as a result, addresses 0x0000 through 0x00ff are mapped modulo style over the entire 64 k external data memory address range. for example, the xram byte at address 0x0000 is shadowed at addresses 0x0100, 0x0200, 0x0300, 0x0400, etc. 8.2.3. special function registers the direct-access data memory locations from 0x80 to 0x ff co nstitute the special fu nction registers (sfrs). the sfrs provide control and data exchange with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to configure and access the sub-systems unique to the mcu. this allo ws the addition of new fu nctionality while retaining compatibility with the mcs-51? instruction set. the sfr registers are accessed anytime the direct addres sing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x 8 (e.g. p0, tcon, scon0, ie, etc.) are bit-addressable as well as byte-addressable. all other sfrs are byte-address able only. unoccupied addresses in the sfr space are reserved for future use. accessing these areas will have an indeter minate effect and should be avoided.
c8051f85x/86x preliminary rev 0.6 49 special function register memory map 9. special function register memory map this section details the specia l function register memory map for the c8051f85x/86x devices. table 9.1. special function register (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 p0mat p0mask vdm0cn f0 b p0mdin p1mdin eip1 - - prtdrv pca0pwm e8 adc0cn0 pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 p1mat p1mask rstsrc e0 acc xbr0 xbr1 xbr2 it01cf - eie1 - d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 crc0in crc0dat adc0pwr d0 psw ref0cn crc0auto crc0cnt p0skip p1skip smb0adm smb0adr c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h crc0cn crc0flip c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth oscicl b8 ip adc0tk - adc0mx adc0cf adc0l adc0h cpt1cn b0 - osclcn adc0cn1 adc0ac - deviceid revid flkey a8 ie clksel cpt1mx cpt1md smb0tc derivid - - a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout - 98 scon0 sbuf0 - cpt0cn pca0clr cpt0md pca0cent cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h pca0pol wdtcn 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph - - - pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable) table 9.2. special function registers register address register description page acc 0xe0 accumulator 115 adc0ac 0xb3 adc0 accumulator configuration 94 adc0cf 0xbc adc0 configuration 93 adc0cn0 0xe8 adc0 control 0 91 adc0cn1 0xb2 adc0 control 1 92 adc0gth 0xc4 adc0 greater-than high byte 99 adc0gtl 0xc3 adc0 greater-than low byte 100 adc0h 0xbe adc0 data word high byte 97 adc0l 0xbd adc0 data word low byte 98
c8051f85x/86x 50 preliminary rev 0.6 special function register memory map adc0lth 0xc6 adc0 less-than high byte 101 adc0ltl 0xc5 adc0 less-than low byte 102 adc0mx 0xbb adc0 multiplexer selection 103 adc0pwr 0xdf adc0 power control 95 adc0tk 0xb9 adc0 burst mode track time 96 b 0xf0 b register 116 ckcon 0x8e clock control 260 clksel 0xa9 clock selection 122 cpt0cn 0x9b comparator 0 control 127 cpt0md 0x9d comparator 0 mode 128 cpt0mx 0x9f comparator 0 multiplexer selection 129 cpt1cn 0xbf comparator 1 control 130 cpt1md 0xab comparator 1 mode 131 cpt1mx 0xaa comparator 1 multiplexer selection 132 crc0auto 0xd2 crc0 automatic control 139 crc0cn 0xce crc0 control 136 crc0cnt 0xd3 crc0 automatic flash sector count 140 crc0dat 0xde crc0 data output 138 crc0flip 0xcf crc0 bit flip 141 crc0in 0xdd crc0 data input 137 derivid 0xad derivative identification 63 deviceid 0xb5 device identification 62 dph 0x83 data pointer low 113 dpl 0x82 data pointer high 112 eie1 0xe6 extended interrupt enable 1 70 eip1 0xf3 extended interrupt priority 1 71 flkey 0xb7 flash lock and key 60 ie 0xa8 interrupt enable 67 ip 0xb8 interrupt priority 69 table 9.2. special function registers (continued) register address register description page
c8051f85x/86x preliminary rev 0.6 51 special function register memory map it01cf 0xe4 int0 / int1 configuration 143 oscicl 0xc7 high frequency oscillator calibration 120 osclcn 0xb1 low frequency oscillator control 121 p0 0x80 port 0 pin latch 192 p0mask 0xfe port 0 mask 190 p0mat 0xfd port 0 match 191 p0mdin 0xf1 port 0 input mode 193 p0mdout 0xa4 port 0 output mode 194 p0skip 0xd4 port 0 skip 195 p1 0x90 port 1 pin latch 198 p1mask 0xee port 1 mask 196 p1mat 0xed port 1 match 197 p1mdin 0xf2 port 1 input mode 199 p1mdout 0xa5 port 1 output mode 200 p1skip 0xd5 port 1 skip 201 p2 0xa0 port 2 pin latch 202 p2mdout 0xa6 port 2 output mode 203 pca0cent 0x9e pca center alignment enable 170 pca0clr 0x9c pca comparator clear control 163 pca0cn 0xd8 pca control 160 pca0cph0 0xfc pca capture module high byte 0 168 pca0cph1 0xea pca capture module high byte 1 174 pca0cph2 0xec pca capture module high byte 2 176 pca0cpl0 0xfb pca capture module low byte 0 167 pca0cpl1 0xe9 pca capture module low byte 1 173 pca0cpl2 0xeb pca capture module low byte 2 175 pca0cpm0 0xda pca capture/compare mode 0 164 pca0cpm1 0xdb pca capture/compare mode 1 171 pca0cpm2 0xdc pca capture/compare mode 1 172 table 9.2. special function registers (continued) register address register description page
c8051f85x/86x 52 preliminary rev 0.6 special function register memory map pca0h 0xfa pca counter/timer low byte 166 pca0l 0xf9 pca counter/timer high byte 165 pca0md 0xd9 pca mode 161 pca0pol 0x96 pca output polarity 169 pca0pwm 0xf7 pca pwm configuration 162 pcon 0x87 power control 75 prtdrv 0xf6 port drive strength 189 psctl 0x8f program store control 59 psw 0xd0 program status word 117 ref0cn 0xd1 voltage reference control 104 reg0cn 0xc9 voltage regulator control 76 revid 0xb6 revision identification 64 rstsrc 0xef reset source 211 sbuf0 0x99 uart0 serial port data buffer 286 scon0 0x98 uart0 serial port control 284 smb0adm 0xd6 smbus0 slave address mask 250 smb0adr 0xd7 smbus0 slave address 249 smb0cf 0xc1 smbus0 configuration 245 smb0cn 0xc0 smbus0 control 247 smb0dat 0xc2 smbus0 data 251 smb0tc 0xac smbus0 timing and pin control 246 sp 0x81 stack pointer 114 spi0cfg 0xa1 spi0 configuration 224 spi0ckr 0xa2 spi0 clock control 226 spi0cn 0xf8 spi0 control 225 spi0dat 0xa3 spi0 data 227 tcon 0x88 timer 0/1 control 262 th0 0x8c timer 0 high byte 266 th1 0x8d timer 1 high byte 267 table 9.2. special function registers (continued) register address register description page
c8051f85x/86x preliminary rev 0.6 53 special function register memory map tl0 0x8a timer 0 low byte 264 tl1 0x8b timer 1 low byte 265 tmod 0x89 timer 0/1 mode 263 tmr2cn 0xc8 timer 2 control 268 tmr2h 0xcd timer 2 high byte 272 tmr2l 0xcc timer 2 low byte 271 tmr2rlh 0xcb timer 2 reload high byte 270 tmr2rll 0xca timer 2 reload low byte 269 tmr3cn 0x91 timer 3 control 273 tmr3h 0x95 timer 3 high byte 277 tmr3l 0x94 timer 3 low byte 276 tmr3rlh 0x93 timer 3 reload high byte 275 tmr3rll 0x92 timer 3 reload low byte 274 vdm0cn 0xff supply monitor control 212 wdtcn 0x97 watchdog timer control 290 xbr0 0xe1 port i/o crossbar 0 186 xbr1 0xe2 port i/o crossbar 1 187 xbr2 0xe3 port i/o crossbar 2 188 table 9.2. special function registers (continued) register address register description page
c8051f85x/86x 54 preliminary rev 0.6 flash memory 10. flash memory on-chip, re-programmable flash memory is included for program code and non-volatile data storage. the flash memory is organized in 512-byte pages. it can be erased and written through the c2 interface or from firmware by overloading the movx instruction. any individual byte in flash memory must only be written once between page erase operations. 10.1. security options the cip-51 provides security options to protect the flash me mory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in re gister psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee mu st be set to 1 before software can erase flash memory. additional security features prevent proprietary program code and dat a constants from being read or altered across the c2 interface. a security lock byte located in flash user space offers pr otection of the flash program memory from access (reads, writes, or erases) by unprotected code or the c2 interface. see section 8. memory organization on page 46 for the location of the security byte. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the 1s complement number represented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are 1) and locked when any other flash pages are locked (any bit of the lock byte is 0). an example is shown in figure 10.1. figure 10.1. security byte decoding the level of flash security depends on the flash acce ss method. the three flash access methods that can be restricted are reads, writes, and erases from the c2 de bug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. table 10.1 summarizes the flash se curity features of the c8051f85x/86x devices. table 10.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages ( e xcept page with lock byte) permitted permitted permitted read, write or erase locked pages ( e xcept page with lock byte) not permitted flash error reset permitted read or write page containing lock byte ( i f no pages are locked) permitted permitted n/a read or write page containing lock byte (if an y p age is locked) not permitted flash error reset permitted read contents of lock byte ( i f no pages are locked) permitted permitted n/a security lock byte: 11111101b 1s complement: 00000010b flash pages locked: 3 (first two flash pages + lock byte page)
c8051f85x/86x preliminary rev 0.6 55 flash memory read contents of lock byte (if any page is locked) not permitted flash error reset permitted erase page containing lock byte ( i f no pages are locked) permitted permitted n/a erase page containing lock byteunlock all p age s (if any page is locked) c2 device erase only f lash error reset flash error reset lock additional pages (cha ng e 1s to 0s in the lock byte) not permitted flash error reset flash error reset unlock individual pages (cha ng e 0s to 1s in the lock byte) not permitted flash error reset flash error reset read, write or erase reserved area not permitted flash error reset flash error reset ? c2 device eraseerases all flash pages in clu d ing the page containing the lock byte. flash error reset not permitted; causes flash error de vice reset (ferror bit in rs tsrc is '1' after reset). ? - all prohibited operations that are per for med via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks the page containing the lock byte. - once written to, the lock byte cannot be modifi e d except by performing a c2 device erase. - if user code writes to the lock byte, the lock do es not t ake effect until the next device reset. table 10.1. flash security summary
c8051f85x/86x 56 preliminary rev 0.6 flash memory 10.2. programming the flash memory writes to flash memory clear bits from logic 1 to logic 0, and can be performed on single byte locations. flash erasures set bits back to logic 1, and occur only on full pages. the write and erase operations are automatically timed by hardware for proper executio n; data polling to determ ine the end of the write/ erase operation is not required. code execution is stalled during a flash write/erase operation. the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programmi ng a non-initialized device. to ensure the integrity of flash contents, it is strongly recommended that the on-chip supply monitor be enabled in any system that includes code that writes and/or erases flash me mory from software. 10.2.1. flash lock and key functions flash writes and erases by user so f t ware are protected with a lock and key function. the flash lock and key register (flkey) must be written with the correct key codes, in sequence, before flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of order, or the wrong codes ar e written, flash writes and er ases will be disabled until the next system reset. flas h writes and erases will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be written again before a following flash operation can be performed. 10.2.2. flash erase procedure the flash memory can be programmed by software usi ng the movx write instruction with the address and data byte to be programmed provided as normal operands. be fore writing to flash memory using movx, flash write operations must be enabled by: (1) setting the pswe program store write enable bit in the psctl register to logic 1 (this directs the movx writes to target flash memory ); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cl eared by software. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire page, perform the following steps: 1. disable interrupts (recommended). 2. set the psee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. 6. using the movx instruction, write a data byte to any location within the page to be erased. 7. clear the pswe and psee bits. 10.2.3. flash write procedure flash bytes are programmed by software with the following sequence: 1 . disable interrupts (recommended). 2. erase the flash page containing the tar get location, as descri bed in section 10.2.2. 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruct ion, write a single data byte to the desired location within the desired page. 8. clear the pswe bit. steps 5C7 must be repeated for each byte to be written. after flash writes are complete, pswe should be cleared so that movx instructions do not target program memory.
c8051f85x/86x preliminary rev 0.6 57 flash memory 10.3. non-volati le data storage the flash memory can be used for non-volatile data stor age as well as program code. this allows data such as calibration coefficients to be calculat ed and stored at run time. data is wri tten using the movx write instruction and read using the movc instruction. note: mo vx read instructions always target xram. 10.4. flash write and erase guidelines any system which contains routines which write or erase fl ash memory from software involves some risk that the write or erase routines will execute unin tentionally if the cpu is operating outside its spec ified operati ng range of supply voltage, system clock frequency or temperature. this accidental execution of flash modifying code can result in alteration of flash memory contents causing a sy stem failure that is only recoverable by re-flashing the code in the device. to help prevent the accidental modification of flash by fi rmware, hardware restricts flash writes and erasures when the supply monitor is not active and selected as a reset source. as the monitor is enabled and selected as a reset source by default, it is recommended that systems writing or erasing flash simply maintain the default state. the following guidelines are recommended for any system whic h contains routines which write or erase flash from code. 10.4.1. voltage supply maintenance and the supply monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to en sure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum su pply rise time specification is met. if the system cannot meet this rise time specification, then add an exter nal supply brownout circuit to the rst pin of the device that holds the device in reset until the voltage supply reaches the lower limi t, and re-asserts rst if the supply drops below the low supply limit. 3. do not disable the supply monitor. if the supply mo nitor must be disabled in the system, firmware should be added to the startup routine to enable the on-chip su pply monitor and enable the supply monitor as a reset source as early in code as possible. this should be the first set of instructions executed after the reset vector. for c-based systems, this may involve modifying the startup code added by the c compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the supply monitor and enabling the supply monitor as a reset source. code examples showing this can be found in an201: writi ng to flash from firmware", availabl e from the silicon laboratories web site. note that the supply monitor must be enabled and enabled as a reset source when writing or erasing flash memory. a flash error reset will occur if either condition is not met. 4. as an added precaution if the supply monitor is ever disabled, explicitly enable the supply monitor and enable the supply monitor as a reset source inside the functions that write and erase flash memory. the supply monitor enable instructions should be placed just after the instruction to set pswe to a 1, but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use direct assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example, "rstsrc = 0x02" is correct. "rstsrc |= 0x02" is incorrect. 6. make certain that all wr ites to the rstsrc register explicitly set the porsf bit to a '1'. areas to check are initialization code which enables ot her reset sources, such as the mi ssing clock detector or comparator, for example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this. 10.4.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (in register psctl) is set to a 1. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one routine in code that sets pswe and psee both to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop variable maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can
c8051f85x/86x 58 preliminary rev 0.6 flash memory be found in an201: writing to flas h from firmware", available from the silicon laboratories web site. 9. disable interrupts prio r to setting pswe to a '1' and leave them disabled until after pswe has been reset to 0. any interrupts posted during th e flash write or erase operation will be serviced in priority order after the flash operation has been completed and inte rrupts have been re-enabled by software. 10. make certain that the flash write and erase pointe r variables are not located in xram. see your compiler documentation for instructions regarding how to exp licitly locate variables in different memory areas. 11. add address bounds checking to the routines that write or erase flash memory to ensure that a routine called with an illegal address does not result in modification of the flash. 10.4.3. system clock 12. if operating from an external crystal-based source , b e advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environmen t, use the internal oscillator or use an external cmos clock. 13. if operating from the external oscillator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed. additional flash recommendations and example code can be found in an201: writing to flash from firmware", available from the silicon laboratories website.
c8051f85x/86x preliminary rev 0.6 59 flash memory 10.5. flash control registers register 10.1. psctl: program store control bit 7 6 5 4 3 2 1 0 name reserved psee pswe typ e r rw rw r e s e t00000000 sfr address: 0x8f table 10.2. psctl register bit descriptions bit name function 7:2 reserved must write reset value. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program mem - ory to be erased. if this bit is logic 1 and f l ash writes are enabled (pswe is logic 1), a write to flash memory using th e movx instruction will erase the entire page that contains the location addressed by the movx instructio n. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of dat a to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruc t ion targets flash memory.
c8051f85x/86x 60 preliminary rev 0.6 flash memory register 10.2. flkey: flash lock and key bit 7 6 5 4 3 2 1 0 name flkey typ e rw r e s e t00000000 sfr address: 0xb7 table 10.3. flkey register bit descriptions bit name function 7:0 flkey flash lock and key register. write: this register provides a lock and key function for flash er asur es and writes. flash writes and erases are enabled by writing 0xa5 followed by 0x f1 to the flkey register. flash writes and erases are automatically disabled af ter the next write or erase is complete. if any writes to flkey are performe d incorrectly, or if a flash write or erase operation is attempted while these operations are disabled, the flash will be permanently locked from writes or erasures until the next device reset. if an applicatio n never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1-0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases are disabled until the next reset.
c8051f85x/86x 62 preliminary rev 0.6 device identification 11. device identification the c8051f85x/86x has sfrs that identify the device family , derivative, and revision. t hese sfrs can be read by firmware at runtime to determine the ca pabilities of the mcu that is executing code. this allows the same firmware image to run on mcus with different memory sizes and pe ripherals, and dynamically change functionality to suit the capabilities of that mcu. 11.1. device identi fication registers register 11.1. deviceid: device identification bit 7 6 5 4 3 2 1 0 name deviceid typ e r r e s e t00110000 sfr address: 0xb5 table 11.1. deviceid register bit descriptions bit name function 7:0 deviceid device id. this read-only register returns the 8 - bit device id: 0x30 (c8051f85x/86x).
c8051f85x/86x preliminary rev 0.6 63 device identification register 11.2. derivid: derivative identification bit 7 6 5 4 3 2 1 0 name derivid typ e r r e s e txxxxxxxx sfr address: 0xad table 11.2. derivid register bit descriptions bit name function 7:0 derivid derivative id. this read-only register returns the 8-bit derivative id, which can be used by firmware to identify which dev ice in the produc t family the code is executing on. 0xd0: c8051f850-gu 0xd1: c8051f851-gu 0xd2: c8051f852-gu 0xd3: c8051f853-gu 0xd4: c8051f854-gu 0xd5: c8051f855-gu 0xe0: c8051f860-gs 0xe1: c8051f861-gs 0xe2: c8051f862-gs 0xe3: c8051f863-gs 0xe4: c8051f864-gs 0xe5: c8051f865-gs 0xf0: c8051f850-gm 0xf1: c8051f851-gm 0xf2: c8051f852-gm 0xf3: c8051f853-gm 0xf4: c8051f854-gm 0xf5: c8051f855-gm
c8051f85x/86x 64 preliminary rev 0.6 device identification register 11.3. revid: revision identifcation bit 7 6 5 4 3 2 1 0 name revid typ e r r e s e txxxxxxxx sfr address: 0xb6 table 11.3. revid register bit descriptions bit name function 7:0 revid revision id. this read-only register returns the 8-bit revision id. 00000000: revision a 00000001: revision b 00000010: revision c 00000011-11111111: reserved.
c8051f85x/86x preliminary rev 0.6 65 interrupts 12. interrupts the c8051f85x/86x includes an extended interrupt system supporting multiple interrup t sources with two priority levels. the allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt- pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt request is generated when the interr upt-pending flag is set. as soon as execution of the current instruction is complete , the cpu generates an lcall to a predetermined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. the interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state. each interrupt source can be individually enabled or disa bled through the use of an associated interrupt enable bit in an sfr (ie and eie1). however, interrupts must first be gl obally enabled by setting the ea bit in the ie register to logic 1 before the individual interrupt enables are recogn ized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu comple tes the return-from-interrupt (reti) instruction, a new interrupt requ est will be generated i mmediately and the cpu will re-enter the isr after the completion of the next instruction. 12.1. mcu interrupt sources and vectors the c8051f85x/86x mcus support interrupt sources for each peripheral on the device. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated and th e cpu will vector to the isr address associ ated with the interrup t-pending flag. mcu interrupt sources, associated vector add resses, priority order and control bits are summarized in table 12.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 12.1.1. interr upt prior ities each interrupt source can be individually programmed to one of two p riority levels: low or high. a low priority interrupt service routine can be preempted by a high pr iority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt pr iority bit in an sfr (ip or eip1) used to configure its priority level. low priority is the def ault. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 12.1. 12.1.2. interr upt l atency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each syste m c lock cycle. therefore, the fastes t possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 cl ock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is executed, a single inst ruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority ) occurs when the cpu is perf orming an reti instruction followed by a div as the next instruction. in this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cycles to co mplete the div inst ruction and 4 clock cycles to execute the lcall to the isr. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. if more than one interrupt is pending when the cpu exits an isr, the cpu will service the next highest priority interrupt that is pending.
c8051f85x/86x 66 preliminary rev 0.6 interrupts table 12.1. interrupt summary interrupt source interrupt vector priority order pending flags bit addressable? cleared by hw? enable flag reset 0x0000 to p none n/a n/a always enabled external interrupt 0 ( int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) external interrupt 1 ( int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) uart0 0x0023 4 ri (scon0.0) ti (scon0.1) y n es0 (ie.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) spi0 0x0033 6 spif (spi0cn.7) ? wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) port match 0x0043 8 none n/a n/a emat (eie1.1) adc0 window compare 0x004b 9 adwint (adc0cn.3) y n ewadc0 (eie1.2) adc0 conversion complete 0x0053 10 adint (adc0cn.5) y n eadc0 (eie1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) covf (pca0pwm.6) y n epca0 (eie1.4) comparator0 0x0063 12 cpfif (cpt0cn.4) c prif (cpt0cn.5) n n ecp 0 (eie1.5) comparator1 0x006b 13 cpfif (cpt1cn.4) c prif (cpt1cn.5) n n ecp 1 (eie1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7)
c8051f85x/86x preliminary rev 0.6 67 interrupts 12.2. interrupt control registers register 12.1. ie: interrupt enable bit 7 6 5 4 3 2 1 0 name ea espi0 et2 es0 et1 ex1 et0 ex0 ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xa8 (bit-addressable) table 12.2. ie register bit descriptions bit name function 7 ea enable all interrupts. globally enables/disables all interrupts and overrides individual interrupt mask settings. 0: disable all in te rr upt sources. 1: enable each interr up t according to its individual mask setting. 6 espi0 enable spi0 interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5 et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua r t 0 interrupt. 3 et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti m e r 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1 et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti m e r 0 interrupt. 1: enable interrupt requests generated by the tf0 flag.
c8051f85x/86x 68 preliminary rev 0.6 interrupts 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. table 12.2. ie register bit descriptions bit name function
c8051f85x/86x preliminary rev 0.6 69 interrupts register 12.2. ip: interrupt priority bit 7 6 5 4 3 2 1 0 name reserved pspi0 pt2 ps0 pt1 px1 pt0 px0 ty per rwrwrwrwrwrwrw r e s e t10000000 sfr address: 0xb8 (bit-addressable) table 12.3. ip register bit descriptions bit name function 7 reserved must write reset value. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. th is bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1 : timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority lev e l. 1: uart0 interrupt set to high priority lev e l. 3 pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1 : timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of th e external interr up t 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. 1 pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1 : timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of th e external interr up t 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level.
c8051f85x/86x 70 preliminary rev 0.6 interrupts register 12.3. eie1: extended interrupt enable 1 bit 7 6 5 4 3 2 1 0 name et3 ecp1 ecp0 epca0 eadc0 ewadc0 emat esmb0 ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xe6 table 12.4. eie1 register bit descriptions bit name function 7 et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by th e comparator 1 cprif or cpfif flags. 5 ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by th e comparator 0 cprif or cpfif flags. 4 epca0 enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupt s . 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversi on complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the adint flag. 2 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (adwint). 1 emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all sm b0 in terrupts. 1: enable interrupt requests generated by smb0.
c8051f85x/86x preliminary rev 0.6 71 interrupts register 12.4. eip1: extended interrupt priority 1 bit 7 6 5 4 3 2 1 0 name pt3 pcp1 pcp0 ppca0 padc0 pwadc0 pmat psmb0 ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xf3 table 12.5. eip1 register bit descriptions bit name function 7 pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. 6 pcp1 comparator1 (cp1) interrupt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 5 pcp0 comparator0 (cp0) interrupt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) in ter rupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2 pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt se t to high priority level. 1 pmat port match interrupt priority control. this bit sets the priority of the port match ev ent interrupt. 0: port match interrupt se t to low priority level. 1 : port match interrupt se t to high priorit y level.
c8051f85x/86x 72 preliminary rev 0.6 interrupts 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb 0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. table 12.5. eip1 register bit descriptions bit name function
c8051f85x/86x 74 preliminary rev 0.6 power management and internal regulator 13. power management and internal regulator all internal circuitry on the c8051f85x/86x devices draw s power from the vdd supply pin. circuits with external connections (i/o pins, analog muxes) are powered directly from the vdd supply voltage, while most of the internal circuitry is supplied by an on-chip ldo regulator. the regulator output is fully internal to the device, and is available also as an adc input or reference source for the comparators and adc. the devices support the standard 8051 power modes: idle and stop. for further power savings in stop mode, the internal ldo regulator may be disabled, shutting do wn the majority of the power nets on the device. although the c8051f85x/86x has idle and stop modes ava ilable, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers and serial buses, have their clocks gated off and draw little power when they are not in use. 13.1. power modes idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and ti mers are inactive, and the internal oscillator is stopped (analog peripherals re main in their selected states; the external oscillator is no t affected). since clocks are running in idle mode, power consumption is dependent upon the system cloc k frequency and the nu mber of peripherals left in active mode before entering idle. stop mode consumes the least power because the majority of the device is shut dow n with no clocks active. the power control register (pcon) is us ed to control the c8051f85x/86x's stop and idle power management modes. 13.1.1. idle mode setting the idle mode select bit (pcon.0) causes the hardw ar e to ha lt the cpu and enter idle mode as soon as the instruction that sets the bit comple tes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode sele ction bit (pcon.0) to be cleared an d the cpu to resume operation. the pending interrupt will be servic ed and the next instruction to be executed after the return from interrupt (reti) will be the instruction immediately following the one that set the id le mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instruction following the write of the idle bit is a single-byte inst ruction and an interrupt occurs during the execution phase of the instruction that se ts the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructions that set the idle bit should be followed by an instruction that has two or more opcode bytes, for example: // in c: pco n |= 0x0 1; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby terminate the idle mode. this feature protects the system from an unin tended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desire d, the wdt may be disabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. this provides the opportunity for additional power savings, allowin g the system to remain in the idle mode indefini tely, waiting for an external stimulus to wake up the system.
c8051f85x/86x preliminary rev 0.6 75 power management and internal regulator 13.1.2. stop mode setting the stop mode select bit (pcon.1) causes the controller core to enter stop mode as soon as the instr uction that sets the bit completes execution. before entering stop mode, the system clock must be sourced by the internal high-frequency oscillator. in stop mode the internal oscillator , cpu, and all digi tal peripherals are stopped; the state of the exte rnal oscillator circuit is not affected. each analog peripheral (i ncluding the external oscillator circuit) may be shut down i ndividually prior to enteri ng stop mode. stop mode ca n only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an intern al reset and thereby terminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. 13.2. ldo regulator c8051f85x/86x devices include an internal regulator that regulates the internal core and logic supply. under default conditions, the intern al regulator will remain on when the devi ce enters stop mode . this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the internal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin and a full power cycle of the device are the only methods of generating a reset. 13.3. power control registers register 13.1. pcon: power control bit 7 6 5 4 3 2 1 0 name gf stop idle ty pe rw rw rw r e s e t00000000 sfr address: 0x87 table 13.1. pcon register bit descriptions bit name function 7:2 gf general purpose flags 5-0. these are general purpose flags fo r use u nder software control. 1 stop stop mode select. setting this bit will place the cip-51 in stop mode. this bit w ill alw ays be read as 0. 0 idle idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0.
c8051f85x/86x 76 preliminary rev 0.6 power management and internal regulator 13.4. ldo control registers register 13.2. reg0cn: voltage regulator control bit 7 6 5 4 3 2 1 0 name reserved stopcf reserved typ e r rw r r e s e t00000000 sfr address: 0xc9 table 13.2. reg0cn register bit descriptions bit name function 7:4 reserved must write reset value. 3 stopcf stop mode configuration. this bit configures the regulator's behavior when the device enters stop mode. 0: regulator is still active in s t op mode. any enabled rese t source will reset the device. 1: regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 2:0 reserved must write reset value.
c8051f85x/86x 78 preliminary rev 0.6 analog-to-digital converter (adc0) 14. analog-to-digital converter (adc0) the adc is a successive-approximation-register (sar) a dc with 12, 10, and 8-bit modes, integrated track-and- hold and a programmable window detector. these different modes allow the user to trade off speed for resolution. adc0 also has an autonomous low power burst mode which can automatically enable adc0, capture and accumulate samples, then place adc0 in a low power shutdown mode without cpu intervention. it also has a 16- bit accumulator that can automatically oversample and average the adc results. the adc is fully configurable under software control via several registers. the adc0 operates in single-ended mode and may be configured to measure different signals using the analog multiplexer. the voltage reference for the adc is selectable between internal and external reference sources. figure 14.1. adc0 functional block diagram adc0 p0 pins (8) p1 pins (8) sar analog to digital converter accumulator window compare sysclk clock divider less than greater than device ground agnd 0.5x C 1x gain control / configuration adc0 vdd vref internal ldo 1.65 v / 2.4 v reference trigger selection adwint (window interrupt) sar clock temp sensor vdd gnd internal ldo input selection adbusy (on demand) timer 0 overflow timer 2 overflow timer 3 overflow cnvstr (external pin) adint (interrupt flag) reference selection
c8051f85x/86x preliminary rev 0.6 79 analog-to-digital converter (adc0) 14.1. adc0 analog multiplexer adc0 on c8051f85x/86x has an analog multiplexer capable of selecting any pin on ports p0 and p1 (up to 16 total), the on-chip temperature sensor, the internal regulated supply, the vdd supply, or gnd. adc0 input channels are selected using the adc0mx register. important note about adc0 input configuration: port pins selected as adc0 inputs should be configured as analog inputs, and should be skipped by the crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmdin and disable the digital driver (pnm dout = 0 and port latch = 1). to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. table 14.1. adc0 input multiplexer channels adc0mx setting signal name qsop24 pin name qfn20 pin name soic16 pin name 00000 adc0.0 p0.0 p0.0 p0.0 00001 adc0.1 p0.1 p0.1 p0.1 00010 adc0.2 p0.2 p0.2 p0.2 00011 adc0.3 p0.3 p0.3 p0.3 00100 adc0.4 p0.4 p0.4 p0.4 00101 adc0.5 p0.5 p0.5 p0.5 00110 adc0.6 p0.6 p0.6 p0.6 00111 adc0.7 p0.7 p0.7 p0.7 01000 adc0.8 p1.0 p1.0 p1.0 01001 adc0.9 p1.1 p1.1 p1.1 01010 adc0.10 p1.2 p1.2 p1.2 01011 adc0.11 p1.3 p1.3 p1.3 01100 adc0.12 p1.4 p1.4 reserved 01101 adc0.13 p1.5 p1.5 reserved 01110 adc0.14 p1.6 p1.6 reserved 01111 adc0.15 p1.7 reserved reserved 10000 temp sensor internal temperature sensor 10001 ldo internal 1.8 v ldo output 10010 vdd vdd supply pin 10011 gnd gnd supply pin 10100-11111 none no connection
c8051f85x/86x 80 preliminary rev 0.6 analog-to-digital converter (adc0) 14.2. adc operation the adc is clocked by an adjustable conversion clock (sarclk). sarclk is a divided version of the selected system clock when burst mode is disabled (adbmen = 0), or a divided version of the high-frequency oscillator when burst mode is enabled (adbmen = 1). the clock divi de value is determined by the adsc bits in the adc0cf register. in most applications, sarclk should be adjusted to operate as fa st as possible, without exceeding the maximum electrical specifications. the sarclk does not directly determine sampling times or sampling rates. 14.2.1. starting a conversion a conversion can be initiated in many ways, depending on th e pr ogrammed states of the adc0 start of conversion mode field (adcm) in register adc0cn0. conversions may be initiated by one of the following: 1. writing a 1 to the adbusy bit of register adc0cn0 (software-triggered) 2. a timer overflow (see the adc0cn0 regist er and the timer section for timer options) 3. a rising edge on the cnvstr input signal (external pin-triggered) writing a 1 to adbusy provides software control of ad c0 whereby conversions are performed "on-demand". all other trigger sources occur autonomous to code executi on. when the conversion is complete, the adc posts the result to its output register and sets the adc interrupt flag (adint). adint may be used to trigger a system interrupts, if enabled, or polled by firmware. during conversion, the adbusy bit is set to logic 1 and re set to logic 0 when the conver sion is complete. however, when polling for adc conversion completions, the adc0 in terrupt flag (adint) should be used instead of the adbusy bit. converted data is available in the adc0 data registers, adc0h:adc0l, when the conversion is complete. important note about using cnvstr: when the cnvstr input is used as the adc0 conversion source, the associated port pin should be skipped in the crossbar settings. 14.2.2. tracking modes each adc0 conversion must be preceded by a minimum tracking time in order for the converted result to be a c curate. the minimum tracking time is given in the electr ical specifications tables. the adtm bit in register adc0cn0 controls the adc0 track-and-hold mode. in its default state when burst mode is disabled, the adc0 input is continuously tracke d, except when a conversion is in progre ss. a conversion will begin immediately when the start-of-conversion trigger occurs. when the adtm bit is logic 1, each conversion is preceded by a tracking period of 4 sar clocks (after the start-of- conversion signal) for any internal (non-cnvstr) conver sion trigger source. when the cnvstr signal is used to initiate conversions with adtm set to 1, adc0 tracks only when cnvstr is lo w; conversion begins on the rising edge of cnvstr (see figure 14.2). setting adtm to 1 is primarily useful when amux settings are frequently changed and conversions are started using the adbusy bit.
c8051f85x/86x preliminary rev 0.6 81 analog-to-digital converter (adc0) figure 14.2. 10-bit adc track and conversi on example ti ming (adbmen = 0) 14.2.3. burst mode burst mode is a power saving feature that allows adc0 to remain in a low power state between conversions. when burst mode is enabled, adc0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or 64 samples using the internal low-power high-freq uency oscillator, then re-enters a low power state. since the burst mode clock is independent of the system clock, adc0 can perform mult iple conversions then enter a low power state within a single system clock cycle, even if t he system clock is slow (e.g. 80 khz). burst mode is enabled by setting adbmen to logic 1. when in burst mode, aden cont rols the adc0 idle power state (i.e. the state adc0 enters when not tracking or perfo rming conversions). if aden is set to logic 0, adc0 is powered down after each burst. if aden is set to logic 1, adc0 remains enabled after each burst. on each convert start signal, adc0 is awaken ed from its idle power state. if adc0 is powered down, it will au tomatically power up and wait the program mable power-up time controlled by the adpwr bits. otherwise, adc0 will start tracking and converting immediately. figure 14.3 shows an example of burst mode operation with a slow system clock and a repeat count of 4. when burst mode is enabled, a single convert start will initiate a number of conversions equa l to the repeat count. when burst mode is disabled, a convert start is required to initiate each conversion. in both modes, the adc0 end of conversion interrupt flag (adint) will be set after repeat count c onversions have been ac cumulated. similarly, the window comparator will not compare th e result to the gr eater-than and less- than registers unt il repeat count conversions have been accumulated. in burst mode, tracking is determined by the settings in adpwr and adtk. settling time requirements may need adjustment in some applications. refer to 14.2.4. se ttling time requirements on page 82 for more details. write '1' to adbusy, timer overflow adtm=1 track convert low power mode adtm=0 track or convert convert track low power or convert sar clocks sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr adtm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track adtm=0 track convert low power mode low power or convert 10 11 12 13 14 123456789 10 11 12 13 14 123456789 10 11 12 13 14 15 16 17 18
c8051f85x/86x 82 preliminary rev 0.6 analog-to-digital converter (adc0) notes: ?? setting adtm to 1 will insert an additional 4 sar clocks of tracking bef ore each conversi on, regardless of the settings of adpwr and adtk. ?? when using burst mode, care must be taken to issue a convert start signal no faster than once every four sysclk periods. this includes extern al convert start signal s. the adc will ignore convert start signals which arrive before a burst is finished. figure 14.3. burst mode tracking example with repeat count set to 4 14.2.4. settling time requirements a minimum amount of tracking time is required before ea ch co nversion can be performed, to allow the sampling capacitor voltage to settle. this tracking time is determined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that when adtm is set to 1, four sar clocks are used for tracking at the start of ever y conversion. large external source impedance will increase the required tracking time. figure 14.4 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 14.1. when measuring any internal source, r total reduces to r mux . see the electrical specification tables for adc0 minimum se ttling time requirements as well as the mux impedance and sampling capacitor values. equation 14.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). convert start adtm = 1 aden = 0 powered down powered down system clock t 4 c power-up and track t c t c t c power-up and track t c.. adtm = 0 aden = 0 powered down powered down c power-up and track t c t c t c power-up and track t c.. adpwr t = tracking set by adtk t4 = tracking set by adtm (4 sar clocks) c = converting adtk t 4 t 4 t 4 t n sa r total c sample ln
c8051f85x/86x preliminary rev 0.6 83 analog-to-digital converter (adc0) figure 14.4. adc0 equivalent input circuits 14.2.5. gain setting the adc has gain settings of 1x and 0.5x . in 1 x mode, the full scale reading of the adc is determined directly by vref. in 0.5x mode, the full-scale reading of the adc occurs when the input voltage is vref x 2. the 0.5x gain setting can be useful to obtain a higher input voltage range when using a small vref voltage, or to measure input voltages that are between vref and vdd. gain settings for the adc are controlled by the adgn bit in register adc0cf. note that even with a gain sett ing of 0.5, voltages above the supply rail cannot be measured directly by the adc. 14.3. 8-bit mode setting the adc08be bit in r egister adc0cf to 1 will put the adc in 8-bi t mode.in 8-bit mode, only the 8 msbs of data are converted, allowing the conversion to be completed in fewer sar clock cycles than a 10-bit conversion. the two lsbs of a conversion are alwa ys 00 in this mode, and the adc0l register will always read back 0x00. 14.4. 12-bit mode when configured for 12-bit conversions, the adc performs four 10-bit conversions usi ng four different reference voltages and combines the results into a single 12-bit value. unlike simple averaging techniques, this method provides true 12-bit resolution of ac or dc input sig nals without depending on noise to provide dithering. the converter also employs a hardware dynamic element matching algorithm that reconfigures the largest elements of the internal dac for each of the four 10-bit conversion s. this reconfiguration cancels any matching errors and enables the converter to achieve 12-bit linearity performance to go along with its 12-bit resolution. the 12-bit mode is enabled by setting the ad12be bit in register adc0ac to logic 1 and configuring the adc in burst mode (adbmen = 1) for four or more conversion s. the conversion can be initiated using any of the conversion start sources, and the 12-bit result will appear in the ad c0h and adc0l registers. since the 12-bit result is formed from a comb ination of four 10-bit results, the maximum output value is 4 x (1023) = 4092, rather than the max value of (2^12 C 1) = 4095 that is produced by a traditional 12-bit converter. to further increase resolution, the burst mode repeat value may be configured to any multiple of four conversions. for example, if a repeat value of 16 is selected, the adc0 output will be a 14-bit number (sum of four 12-bit numbers) with 13 effective bits of resolution. the ad12sm bit in register adc0tk controls when the adc will track and samp le the input signal. when ad12sm is set to 1, the selected input signal will be tracked before the first conversi on of a set and held internally during all four conversions. when ad12sm is clear ed to 0, the adc will track and sample the selected input before each of the four conversions in a set. when maximum throughp ut (180-200 ksps) is needed, it is recommended that ad12sm be set to 1 and adtk to 0x3f, and that the ad c be placed in always-on mode (aden = 1). for sample rates under 180 ksps, or when accumulating multiple sa mples, ad12sm should normally be cleared to 0, and adtk should be configured to provide the appropri ate settling time for the subsequent conversions. r mux c sample rc input = r mux * c sample mux select p0.x note: the value of csample depends on the pga gain. see electrical specifications for details.
c8051f85x/86x 84 preliminary rev 0.6 analog-to-digital converter (adc0) 14.5. power considerations the adc has several power-saving features which can help the user optimize power c onsumption according to the needs of the application. the most efficient way to use the adc for slower sample rates is by using burst mode. burst mode dynamically controls power to the adc and (if used) the internal voltage reference. by completely powering off these circuits when the adc is not tracking or converting, the average supply current required for lower sampling rates is reduced significantly. the adc also provides low power opti ons that allow reduction in operating current when operating at low sar clock frequencies or with longer tracking times. the inte rnal common-mode buffer can be configured for low power mode by setting the adlpm bit in adc0pwr to 1. two other fields in the adc0pwr register (adbias and admxlp) may be used together to adjust the power consumed by the adc and its multiplexer and reference buffers, respectively. in general, these options are us ed together, when operating with a sar conversion clock frequency of 4 mhz. table 14.2. adc0 optimal power configuration (8 and 10-bit mode) required throughput reference source mode configuration sar clock speed other register field settings 325-800 ksps any always-on (a den = 1 adbmen = 0) 12.25 mhz (adsc = 1) adc0pwr = 0x40 adc0tk = n/a adrpt = 0 0-325 ksps external burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 0 250-325 ksps internal burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 0 200-250 ksps internal always-on (aden = 1 adbmen = 0) 4.08 mhz (adsc = 5) adc0pwr = 0xf0 adc0tk = n/a adrpt = 0 0-200 ksps internal burst mode (aden = 0 adbmen = 1) 4.08 mhz (adsc = 5) adc0pwr = 0xf4 adc0tk = 0x34 adrpt = 0 notes: 1. for always-on configuration, adsc setti ngs assume sysclk is the internal 24.5 mhz high-frequency oscillator. adju st adsc as needed if using a different source for sysclk. 2. adrpt reflects the minimum setting for this bit field. when using the adc in burst mode, up to 64 samples may be au to-accumulated per conversion start by adjusting adrpt.
c8051f85x/86x preliminary rev 0.6 85 analog-to-digital converter (adc0) for applications where burst mode is used to automatically accumula te multiple results, ad ditional supply current savings can be realized. the length of time the adc is ac tive during each burst contains power-up time at the beginning of the burst as well as the conversion time required for each conversion in the burst. the power-on time is only required at the beginning of each burst. when co mpared with single-sample bursts to collect the same number of conversions, mult i-sample bursts will consume significantly less power. for example, performing an eight-cycle burst of 10-bt c onversions consumes about 61 % of the power required to perform those same eight samples in single-cycle bursts. for 12-bit conversions, an eight-cycle burst results in about 85% of the equivalent single-cycle bursts. figure 14.5 shows this relationship for the different burst cycle lengths. see the electrical characteristics chapter for details on power consumption and the maximum clock frequencies allowed in each mode. table 14.3. adc0 optimal power configuration (12-bit mode) required throughput reference source mode configuration sar clock speed other register field settings 180-200 ksps any always -on + bu rst mode (aden = 1 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x40 adc0tk = 0xbf adrpt = 1 125-180 ksps any always-on + burst mode (aden = 1 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x40 adc0tk = 0x3a adrpt = 1 0-125 ksps external burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 1 50-125 ksps internal burst mode (aden = 0 adbmen = 1) 12.25 mhz (adsc = 1) adc0pwr = 0x44 adc0tk = 0x3a adrpt = 1 0-50 ksps internal burst mode (aden = 0 adbmen = 1) 4.08 mhz (adsc = 5) adc0pwr = 0xf4 adc0tk = 0x34 adrpt = 1 notes: 1. adrpt reflects the minimum setting for this bit field. when using the adc in burst mode, up to 64 samples may be au to-accumulated per conversion trigger by adjusting adrpt.
c8051f85x/86x 86 preliminary rev 0.6 analog-to-digital converter (adc0) figure 14.5. burst mode accumulation power savings 14.6. output code formatting the registers adc0h and adc0l contain the high and low by tes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the adsjst field. when the repeat count is set to 1 in 10-bit mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. example codes are shown below for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to 0. when the repeat count is greater than 1, th e ou tput conversion code repr esents the accumulated result of the conversions performed and is updated after the last conversion in the series is finished. sets of 4, 8, 16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. the repeat count can be selected using the adrpt bits in the adc0ac register. when a repeat count higher than 1, the adc output must be right-justified (adsjst = 0xx); unused bits in the ad c0h and adc0l registers are set to 0. the example below shows the right-justified result fo r various input voltages and repeat counts. notice that accumulating 2 n samples is equivalent to left-shifting by n bit positions when all sa mples returned fr om the adc have the same value. the adsjst bits can be used to format th e contents of the 16-bit accumulator. the accumulated result can be shifted right by 1, 2, or 3 bit positions. based on the principles of oversampling and averaging, the effective adc resolution increases by 1 bit each time the oversampling ra te is increased by a factor of 4. the example below shows how to increase the effective adc resolution by 1, 2, and 3 bits to obtain an effective adc resolution of 11- bit, 12-bit, or 13-bit respecti vely without cp u intervention. input voltage right-justified adc0h:adc0l (adsjst = 000) left-justified adc0h:adc0l (adsjst = 100) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage repeat count = 4 repeat count = 16 repeat count = 64 v ref x 1023/1024 0x0ffc 0x3ff0 0xffc0 v ref x 512/1024 0x0800 0x2000 0x8000 v ref x 511/1024 0x07fc 0x1ff0 0x7fc0 0 0x0000 0x0000 0x0000 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 1 2 4 8 16 32 64 average current compared to single r cycle number of cycles accumulated in burst 10r bit burst mode power 80% 82% 84% 86% 88% 90% 92% 94% 96% 98% 100% 12481 6 average current compared to singler cycle number of cycles accumulated in burst 12rbit burst mode power
c8051f85x/86x preliminary rev 0.6 87 analog-to-digital converter (adc0) 14.7. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. this is especia lly effective in an interrupt- driven system, saving code space and cpu bandwidth while delivering faster system re sponse times. the window detector interrupt flag (adwint in register adc0cn0) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison values. the window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the a dc0 less-than and adc0 greater-than registers. 14.7.1. window detector in si ngle-ended mode figure 14.6 shows two example window comparisons for ri ght-justified data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned in teger value. in the left example, an adwint interrupt will be generated if the adc0 co nversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0lt l (if 0x0040 < adc0h:adc0l < 0x0 080). in the right example, and adwint interrupt will be generated if th e adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or a dc0h:adc0l > 0x0080). figure 14.7 shows an example using left-justified data with the same comparison values. figure 14.6. adc window compare example: right-justified single-ended data input voltage repeat count = 4 shift right = 1 11-bit result repeat count = 16 shift right = 2 12-bit result repeat count = 64 shift right = 3 13-bit result v ref x 1023/1024 0x07f7 0x0ffc 0x1ff8 v ref x 512/1024 0x0400 0x0800 0x1000 v ref x 511/1024 0x03fe 0x04fc 0x0ff8 0 0x0000 0x0000 0x0000 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint=1 adwint not affected adwint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint not affected adwint=1 adwint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl
c8051f85x/86x 88 preliminary rev 0.6 analog-to-digital converter (adc0) figure 14.7. adc window compare example: left-justified single-ended dat a 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint=1 adwint not affected adwint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) adwint not affected adwint=1 adwint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
c8051f85x/86x preliminary rev 0.6 89 analog-to-digital converter (adc0) 14.8. voltage and gr ound reference options the voltage reference multiplexer is c onfigurable to use an externally connected voltage reference, the internal voltage reference, or one of two power supply voltages. the ground reference mux allows the ground reference for adc0 to be selected between the ground pin (gnd) or a port pin dedicated to analog ground (agnd). the voltage and ground reference options ar e configured using the ref0cn register. important note about the vref and agnd inputs: port pins are used as the external vref and agnd inputs. when using an external voltage reference, vref should be configured as an analog input and skipped by the digital crossbar. when using agnd as the ground referenc e to adc0, agnd should be configured as an analog input and skipped by the digital crossbar. 14.8.1. external vo l tage reference to use an external voltage reference, refsl should be set to 00. bypass capacitors should be added as re commended by the manufacturer of the external vo ltage reference. if the manufacturer does not provide recommendations, a 4.7uf in parallel with a 0.1uf capacitor is recommended. 14.8.2. internal vo l tage reference for applications requiring the maximum number of port i/o pins , or very short vref turn-on time, the high-speed reference will be the best internal refe rence option to choose. the internal reference is selected by setting refsl to 11. when selected, the internal reference will be automatically enabled/disabled on an as-needed basis by the adc. the reference can be set to one of two voltage values: 1.65 v or 2.4 v, depending on the value of the ireflvl bit. for applications with a non-varying power supply voltag e, using the power supply as the voltage reference can provide the adc with added dynamic range at the cost of reduced power supply noise rejection. to use the external supply pin (vdd) or the 1.8 v regulated digita l supply voltage as the reference source, refsl should be set to 01 or 10, respectively. internal reference sources are not routed to the vref pin, and do not require external capacitors. the electrical specifications tables detail sar clock and thro ughput limitations for each reference source. 14.8.3. analog ground reference to prevent ground noise generated by switching digital logic fro m affecting sensitive analog measurements, a separate analog ground reference option is available. when enabled, the ground reference for the adc during both the tracking/sampling and the conversion periods is taken from the agnd pin. any external sensors sampled by the adc should be referenced to the agnd pin. if an external voltage reference is used, the agnd pin should be connected to the ground of the external reference and its associated decoupling capacitor. the separate analog ground reference option is enabled by setting gndsl to 1. note that when sampling the internal temperature sensor, the internal chip ground is always used for the sa mpling operation, regardless of the setting of the gndsl bit. similarly, whenever the internal 1.65 v high-speed reference is selected, the internal chip ground is always used during the conversion period, regardless of the setting of the gndsl bit.
c8051f85x/86x 90 preliminary rev 0.6 analog-to-digital converter (adc0) 14.9. temperature sensor an on-chip temperature sensor is included, which can be di rectly accessed via the adc multiplexer in single-ended configuration. to use the adc to measure the temperature sensor, the adc mux channel should select the temperature sensor. the temperature sensor transfer fu nction is shown in figure 14.8. the output voltage (v temp ) is the positive adc input when the a dc multiplexer is set correctly. the tempe bit in register ref0cn enables/ disables the temperature sensor. while disabled, the temp erature sensor defaults to a high impedance state and any adc measurements performed on the sensor will result in meaningle ss data. refer to the electrical specification tables for the slope and offset parameters of the temperature sensor. figure 14.8. temperature sensor transfer function 14.9.1. calibration the uncalibrated temperature sensor output is extr emel y linear and suitable for relative temperature measurements. for absolute temperature measurements, of fset and/or gain calibration is recommended. typically a 1-point (offset) calibration includes the following steps: 1. control/measure the ambient temperat ure (this temperature must be known). 2. power the device, and delay for a few seconds to allo w for self-heating. 3. perform an adc conversion with the te mperature sensor selected as the adc input. 4. calculate the offset characteri stics, and store this value in non-v olatile memory for use with subsequent temperature sensor measurements. temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope
c8051f85x/86x preliminary rev 0.6 91 analog-to-digital converter (adc0) 14.10. adc control registers register 14.1. adc0cn0: adc0 control 0 bit 7 6 5 4 3 2 1 0 name aden adbmen adint adbusy adwint adcm ty pe rw rw rw rw rw rw r e s e t00000000 sfr address: 0xe8 (bit-addressable) table 14.4. adc0cn0 register bit descriptions bit name function 7 aden enable. 0: adc0 disabled (low-power shutdown). 1: adc0 enabled (active and re ady for da ta conversions). 6 adbmen burst mode enable. 0: adc0 burst mode disabled. 1: adc0 burst mo de enabled. 5 adint conversion complete interrupt flag. set by hardware upon completion of a data conversion (adbmen=0), or a burst of con - versions (adbmen=1). can trigger an interrupt. must be cleared by software. 4 adbusy adc busy. writing 1 to this bit initiates an adc conv er sion wh en adc0cm = 000. this bit should not be polled to indicate when a conversion is complete. instead, the adint bit should be used when polling for conversion completion. 3 adwint window compare interrupt flag. set by hardware when the contents of adc0 h:adc0l fall within the window s p ecified by adc0gth:adc0gtl and adc0lth:adc0ltl. can trigge r an interrupt. must be cleared by software. 2:0 adcm start of conversion mode select. specifies the adc0 start of conversion so ur ce . all remaining bit combinations are reserved. 000: adc0 conversion initiat ed on write of 1 to adbusy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 3. 100: adc0 conversion initiated on rising edge of cnvstr. 101-111: reserved.
c8051f85x/86x 92 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.2. adc0cn1: adc0 control 1 bit 7 6 5 4 3 2 1 0 name reserved adcmbe typ e r rw r e s e t00000000 sfr address: 0xb2 table 14.5. adc0cn1 register bit descriptions bit name function 7:1 reserved must write reset value. 0 adcmbe common mode buffer enable. 0: disable the common mode buffer. this setting should be used only if the tracking time o f the signal is greater than 1.5 us. 1: enable the common mode buff er. this setting should be us ed in most cases, and will give the best dynamic adc performance. the common mode buffer must be enabled if signal tracking time is less than or equal to 1.5 us.
c8051f85x/86x preliminary rev 0.6 93 analog-to-digital converter (adc0) register 14.3. adc0cf: adc0 configuration bit 7 6 5 4 3 2 1 0 name adsc ad8be adtm adgn ty pe rw rw rw rw r e s e t11111000 sfr address: 0xbc table 14.6. adc0cf register bit descriptions bit name function 7:3 adsc sar clock divider. this field sets the adc clock divider value. it sh ou ld be configured to be as close to the maximum sar clock speed as the datasheet will allow. the sar clock frequency is given by the following equation: f adcclk is equal to the selected sysclk when adbmen is 0 and the high-frequency oscillator when adbmen is 1. 2 ad8be 8-bit mode enable. 0: adc0 operates in 10-bit or 12-bit mode (normal operation). 1: adc0 operates in 8-bit mode. 1 adtm track mode. selects between normal or delayed tracking modes. 0: normal track mode. when adc0 is enabled, conversion begins immediately following the st art-of-conversion signal. 1: delayed track mode. when adc0 is enab led, conversion be gins 4 sar clock cycles following the start-of-conversion signal. the adc is allowed to track during this time. 0 adgn gain control. 0: the on-chip pga gain is 0.5. 1: the on-chip pga gain is 1. f clksar f adcclk adsc 1 + ------------------------ - =
c8051f85x/86x 94 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.4. adc0ac: adc0 accumulator configuration bit 7 6 5 4 3 2 1 0 name ad12be adae adsjst adrpt ty pe rw rw rw rw r e s e t00000000 sfr address: 0xb3 table 14.7. adc0ac register bit descriptions bit name function 7 ad12be 12-bit mode enable. enables 12-bit mode. in 12-bit mode, the adc throughput is reduced by a factor of 4. 0: 12-bit mode disabled. 1: 12-bit mode enabled. 6 adae accumulate enable. enables multiple conversions to be accumulated when burst mode is disabled. 0: adc0h:adc0l contain the result of the la te st conversion when burst mode is dis - abled. 1: adc0h:adc0l contain the accumulated conv er sion results when burst mode is dis - abled. software must write 0x0000 to adc0h:adc0l to clear the accumulated result. 5:3 adsjst accumulator shift and justify. specifies the format of data read from adc0h:adc0l. all remaining bit combinations ar e reserved. 000: right justified. no shifting applied. 001: right justified. shifted right by 1 bit. 010: right justified. shifted right by 2 bits. 011: right justified. shifted right by 3 bits. 100: left justified. no shifting applied. 101-111: reserved. 2:0 adrpt repeat count. selects the number of conversions to perform an d accumulate in burst mode. this bit field must be set to 000 if burst mode is disabled. 000: perform and accumulate 1 conversion (not used in 12-bit mode). 001: perform and accumulate 4 conversions (1 conversion in 12-bit mode). 010: perform and accumulate 8 conversions (2 conversions in 12-bit mode). 011: perform and accumulate 16 conversions (4 conversions in 12-bit mode). 100: perform and accumulate 32 conver sions (8 conv ersions in 12-bit mode). 101: perform and accumulate 64 conver sions (1 6 co nversions in 12-bit mode). 110-111: reserved.
c8051f85x/86x preliminary rev 0.6 95 analog-to-digital converter (adc0) register 14.5. adc0pwr: adc0 power control bit 7 6 5 4 3 2 1 0 name adbias admxlp adlpm adpwr ty pe rw rw rw rw r e s e t00001111 sfr address: 0xdf table 14.8. adc0pwr register bit descriptions bit name function 7:6 adbias bias power select. this field can be used to adjust the adc' s power co nsumption based on the conversion speed. higher bias currents allow for faster conversion times. 00: select bias current mode 0. recommended to use modes 1, 2, or 3. 01: select bias current mode 1 (sarclk <= 16 mhz). 10: select bias current mode 2. 11: select bias current mode 3 (sarclk <= 4 mhz). 5 admxlp mux and reference low power mode enable. enables low power mode operation for the multiplexer and voltage reference buffers. 0: low power mode disabled. 1: low power mode enabled (sar clock < 4 mhz). 4 adlpm low power mode enable. this bit can be used to reduce power to the adc's internal common mode buffer. it can b e set to 1 to reduce power when tracking times in the application are longer (slower sample rates). 0: disable low power mode. 1: enable low power mode (requires extended tracking time). 3:0 adpwr burst mode power up time. this field sets the time delay allowed for t he adc to po we r up from a low power state. when adtm is set, an additional 4 sarclks are added to this time. t pwrtime 8adpwr ? f hfosc ------------------------------ =
c8051f85x/86x 96 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.6. adc0tk: adc0 burst mode track time bit 7 6 5 4 3 2 1 0 name ad12sm reserved adtk ty pe rw rw rw r e s e t00011110 sfr address: 0xb9 table 14.9. adc0tk register bit descriptions bit name function 7 ad12sm 12-bit sampling mode. this bit controls the way that the adc sample s the in put when in 12-bit mode. when the adc is configured for multiple 12-bit conver sions in burst mode, the ad12sm bit should be cleared to 0. 0: the adc will re-track and sa mple the input four times during a 12-bit conversion. 1: the adc will sample the input once at the beginning of each 12-bit c onversion. the adtk field can be set to 63 to maximize throughput. 6 reserved must write reset value. 5:0 adtk burst mode tracking time. this field sets the time delay between co nsecutive co nver sions performed in burst mode. when adtm is set, an additio nal 4 sarclks are added to this time. the burst mode track delay is not inserted prior to the first conversion. the required tracking t ime for the first conversion should be defined with the adpwr field. t bmtk 64 adtk C f hfosc ---------------------------- =
c8051f85x/86x preliminary rev 0.6 97 analog-to-digital converter (adc0) register 14.7. adc0h: adc0 data word high byte bit 7 6 5 4 3 2 1 0 name adc0h typ e rw r e s e t00000000 sfr address: 0xbe table 14.10. adc0h register bit descriptions bit name function 7:0 adc0h data word high byte. when read, this register returns the most sig n ificant byte of the 16-bit adc0 accumula - tor, formatted according to t h e settings in adsjst. the re gister may also be written, to set the upper byte of the 16-bit adc0 accumulator. note: if accumulator shifting is enabled, the most significant bits of the value read will be zeros. this register should not be written when the sync bit is set to 1.
c8051f85x/86x 98 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.8. adc0l: adc0 data word low byte bit 7 6 5 4 3 2 1 0 name adc0l typ e rw r e s e t00000000 sfr address: 0xbd table 14.11. adc0l register bit descriptions bit name function 7:0 adc0l data word low byte. when read, this register returns the least significan t byte of the 16-bit adc0 accumula - tor, formatted according to t h e settings in adsjst. the re gister may also be written, to set the lower byte of the 16-bit adc0 accumulator. note: if accumulator shifting is enabled, the most significant bits of the value read will be zeros. this register should not be written when the sync bit is set to 1.
c8051f85x/86x preliminary rev 0.6 99 analog-to-digital converter (adc0) register 14.9. adc0gth: adc0 greater-than high byte bit 7 6 5 4 3 2 1 0 name adc0gth typ e rw r e s e t11111111 sfr address: 0xc4 table 14.12. adc0gth register bit descriptions bit name function 7:0 adc0gth greater-than high byte. most significant byte of the 16-bit greater-than window compare register.
c8051f85x/86x 100 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.10. adc0gtl: adc0 greater-than low byte bit 7 6 5 4 3 2 1 0 name adc0gtl typ e rw r e s e t11111111 sfr address: 0xc3 table 14.13. adc0gtl register bit descriptions bit name function 7:0 adc0gtl greater-than low byte. least significant byte of the 16-bit greater-than window compare register. note: in 8-bit mode, this register should be set to 0x00.
c8051f85x/86x preliminary rev 0.6 101 analog-to-digital converter (adc0) register 14.11. adc0lth: adc0 less-than high byte bit 7 6 5 4 3 2 1 0 name adc0lth typ e rw r e s e t00000000 sfr address: 0xc6 table 14.14. adc0lth register bit descriptions bit name function 7:0 adc0lth less-than high byte. most significant byte of the 16-bit less-than window compare register.
c8051f85x/86x 102 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.12. adc0ltl: adc0 less-than low byte bit 7 6 5 4 3 2 1 0 name adc0ltl typ e rw r e s e t00000000 sfr address: 0xc5 table 14.15. adc0ltl register bit descriptions bit name function 7:0 adc0ltl less-than low byte. least significant byte of the 16-bit le ss- than window compare register. note: in 8-bit mode, this register should be set to 0x00.
c8051f85x/86x preliminary rev 0.6 103 analog-to-digital converter (adc0) register 14.13. adc0mx: adc0 multiplexer selection bit 7 6 5 4 3 2 1 0 name reserved adc0mx typ e r rw r e s e t00011111 sfr address: 0xbb table 14.16. adc0mx register bit descriptions bit name function 7:5 reserved must write reset value. 4:0 adc0mx amux0 positive input selection. selects the positive input channel for adc0. fo r reserved bit comb inations, no input is selected. 00000: adc0.0 00001: adc0.1 00010: adc0.2 00011: adc0.3 00100: adc0.4 00101: adc0.5 00110: adc0.6 00111: adc0.7 01000: adc0.8 01001: adc0.9 01010: adc0.10 01011: adc0.11 01100: adc0.12 01101: adc0.13 01110: adc0.14 01111: adc0.15 10000: temperature sensor. 10001: internal ldo regulator output. 10010: vdd 10011: gnd 10100-11111: reserved.
c8051f85x/86x 104 preliminary rev 0.6 analog-to-digital converter (adc0) register 14.14. ref0cn: voltage reference control bit 7 6 5 4 3 2 1 0 name ireflvl reserved gnds l r efsl tempe reserved t y p er wrr wr wr w r r e s e t00011000 sfr address: 0xd1 table 14.17. ref0cn register bit descriptions bit name function 7 ireflvl internal voltage reference level. sets the voltage level for the internal reference source. 0: the internal reference operates at 1.65 v nominal. 1: the internal reference operates at 2.4 v nominal. 6 reserved must write reset value. 5 gndsl analog ground reference. selects the adc0 ground reference. 0: the adc0 ground reference is the gnd pin. 1: the adc0 ground reference is the agnd pin. 4:3 refsl voltage reference select. selects the adc0 voltage reference. 00: the adc0 voltage reference is the vref pin. 01: the adc0 voltage reference is the vdd pin. 10: the adc0 voltage reference is the internal 1.8 v digital supply voltage. 11: the adc0 voltage reference is the internal voltage reference. 2 tempe temperature sensor enable. enables/disables the internal temperature sensor. 0: temperature sensor disabled. 1: temperature sensor enabled. 1:0 reserved must write reset value.
c8051f85x/86x 106 preliminary rev 0.6 cip-51 microcontroller core 15. cip-51 microcontroller core the c8051f85x/86x uses the cip-51 microcontroller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the mcu family has a superset of all the peripherals included with a standard 8051. the cip-51 also includes on-chip debug hardware and interfaces directly with the analog and digital sub systems providing a complete data acquisition or control- system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see figure 15 .1 for a block diagram). the cip-51 includes the following features: 15.1. performance the cip-51 employs a pipelined architecture that greatl y increases its instruction throughput over the standard 8051 architecture. the cip-51 core ex ecutes 70% of its instructions in on e or two system clock cycles, with no instructions taking more than eight system clock cycles. figure 15.1. cip-51 block diagram with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total numb er of instructions that re quire each execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 ?? fully compatible with mc s-51 instruction set ?? 25 mips peak throughput with 25 mhz clock ?? 0 to 25 mhz clock frequency ?? extended interrupt handler ?? reset input ?? power management modes ?? on-chip debug logic ?? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
c8051f85x/86x preliminary rev 0.6 107 cip-51 microcontroller core 15.2. programming and debugging support in-system programming of the flash program memory an d communication with on-chip debug support logic is accomplished via the silicon labs 2- wire development interface (c2). the on-chip debug s upport logic facilitates full spe ed in-circuit debugg ing, allowing the se tting of hardware breakpoints, starting, stopping and single stepping through program exec ution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. this method of on-chip debugging is completely non-intrusiv e, requiring no ram, stack, timers, or other on-chip resources. the cip-51 is supported by de velopment tools from silicon labs and third party vendors. silicon labs provides an integrated development environment (ide ) including editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to prov ide fast and efficient in -system device programming and debugging. third party macro assemblers and c compilers are also available. 15.3. instruction set the instruction set of the cip-51 syst em controller is fully compatible with the standard mcs-51? instruction set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and functional equivalent of their mcs-51? counter parts, including opcodes, addressing modes and effect on psw flags. however, instruction timing is different than that of the standard 8051. 15.3.1. instruction and cpu timing in many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. howe ver, the cip-51 implementation is based solely on clock cycle timing. all instruction timings ar e specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most inst ructions execute in the same number of clock cycles as there are program bytes in the instruct ion. conditional branch instructions ta ke one less clock cycle to complete when the branch is not taken as opposed to when the bran ch is taken. table 15.1 is the cip-51 instruction set summary, which includes the mnemonic, number of byte s, and number of clock cycles for each instruction.
c8051f85x/86x 108 preliminary rev 0.6 cip-51 microcontroller core table 15.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1
c8051f85x/86x preliminary rev 0.6 109 cip-51 microcontroller core xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 table 15.1. cip-51 instruction set summary mnemonic description bytes clock cycles
c8051f85x/86x 110 preliminary rev 0.6 cip-51 microcontroller core xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 15.1. cip-51 instruction set summary mnemonic description bytes clock cycles
c8051f85x/86x preliminary rev 0.6 111 cip-51 microcontroller core notes on registers, operands and addressing modes: rn register r0Cr7 of the currently selected register bank. @ri data ram location addressed indirectly through r0 or r1. rel 8-bit, signed (twos complement) offset relative to the first byte of the following in struction. used by sjmp and all conditional jumps. direct 8-bit internal data locations address. this could be a direct-access data ram location (0x00C0x7f) or an sfr (0x80C0xff). #data 8-bit constant #data16 16-bit constant bit direct-accessed bit in data ram or sfr addr11 11-bit destination address used by acall and ajmp . the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 16-bit destination address used by lcall and lj mp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
c8051f85x/86x 112 preliminary rev 0.6 cip-51 microcontroller core 15.4. cpu core registers register 15.1. dpl: data pointer low bit 7 6 5 4 3 2 1 0 name dpl typ e rw r e s e t00000000 sfr address: 0x82 table 15.2. dpl register bit descriptions bit name function 7:0 dpl data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed flash memory or xram.
c8051f85x/86x preliminary rev 0.6 113 cip-51 microcontroller core register 15.2. dph: data pointer high bit 7 6 5 4 3 2 1 0 name dph typ e rw r e s e t00000000 sfr address: 0x83 table 15.3. dph register bit descriptions bit name function 7:0 dph data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed flash memory or xram.
c8051f85x/86x 114 preliminary rev 0.6 cip-51 microcontroller core register 15.3. sp: stack pointer bit 7 6 5 4 3 2 1 0 name sp typ e rw r e s e t00000111 sfr address: 0x81 table 15.4. sp register bit descriptions bit name function 7:0 sp stack pointer. the stack pointer holds the location of the to p of the st ack. the stack pointer is incre - mented before every push operation. the sp r egister defaults to 0x07 after reset.
c8051f85x/86x preliminary rev 0.6 115 cip-51 microcontroller core register 15.4. acc: accumulator bit 7 6 5 4 3 2 1 0 name acc typ e rw r e s e t00000000 sfr address: 0xe0 (bit-addressable) table 15.5. acc register bit descriptions bit name function 7:0 acc accumulator. this register is the accumulator for arithmetic operations.
c8051f85x/86x 116 preliminary rev 0.6 cip-51 microcontroller core register 15.5. b: b register bit 7 6 5 4 3 2 1 0 name b typ e rw r e s e t00000000 sfr address: 0xf0 (bit-addressable) table 15.6. b register bit descriptions bit name function 7:0 b b register. this register serves as a second accumu lator fo r certain arithmetic operations.
c8051f85x/86x preliminary rev 0.6 117 cip-51 microcontroller core register 15.6. psw: program status word bit 7 6 5 4 3 2 1 0 name cy ac f0 rs ov f1 parity ty pe rw rw rw rw rw rw r r e s e t00000000 sfr address: 0xd0 (bit-addressable) table 15.7. psw register bit descriptions bit name function 7 cy carry flag. this bit is set when the last arithmetic operatio n r e sulted in a carry (addition) or a borrow (subtraction). it is cleared to logic 0 by all other arithmetic operations. 6 ac auxiliary carry flag. this bit is set when the last ar ithme tic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith - metic operations. 5 f0 user flag 0. this is a bit-addressable, general purpose flag for use under software control. 4:3 rs register bank select. these bits select which register ban k is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2 ov overflow flag. this bit is set to 1 under the following circumstances: 1. an add, addc, or subb instruct ion caus es a sign-change overflow. 2. a mul instruction results in an overflow (result is greater than 255). 3. a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div instructions in all ot her cases. 1 f1 us er flag 1. this is a bit-addressable, general purpose flag for use under software control. 0 parity parity flag. this bit is set to logic 1 if the sum of the ei ght bit s in the accumulator is odd and cleared if the sum is even.
c8051f85x/86x 118 preliminary rev 0.6 clock sources and selection (hfosc0, lfosc0, and extclk) 16. clock sources and selection (hfosc0, lfosc0, and extclk) the c8051f85x/86x devices can be cloc ked from the internal low power 24.5 mhz oscillator, the internal low- frequency 80 khz oscillator, or an external cmos clock signal at the extclk pin. an adjustable clock divider allows the selected clock sour ce to be post-scaled by powers of 2, up to a factor of 128. by default, the system clock comes up as the 24.5 mhz oscillator divided by 8. figure 16.1. clocking options 16.1. programmable hi gh-frequency oscillator all c8051f85x/86x devices in clude a programmable internal high-frequency oscillator th at defaults as the system clock after a system reset. the oscillator is automatically enabled when it is requested. the internal oscillator period can be adjusted via the oscicl register. on c8051f85x/ 86x devices, oscicl is factory calibrated to obtain a 24.5 mhz base frequency. 16.2. programmable low-frequency oscillator a programmable low-fr equency internal oscillator is also included. the lo w-frequency oscillator is calibrated to a nominal frequency of 80 khz. a divider at the oscillator output is capable of dividing the output clock of the module by 1, 2, 4, or 8, using the oscld bits in the osclcn register. additionally, the osclf bits can be used to coarsely adjust the oscilla tors output frequency. 16.2.1. calibrating the internal l-f o scillator timer 3 includes a capture function th at can be used to capture the oscilla tor frequency , when running from a known time base. when timer 3 is conf igured for l-f oscillator capture mode, a rising ed ge of the low-frequency oscillators output will cause a capture event on the corresponding timer. as a capture event oc curs, the current timer value (tmr3h:tmr3l) is copied into the timer reload registers (tmr3rlh:tmr3rll). by recording the difference between two successive time r capture values, the low- frequency oscillators period can be calculated. the osclf bits can then be adjusted to produce the desired oscillator frequency. 16.3. external clock an external cmos clock source is also supported by the c8051f85x/86x family. the extclk pin on the device serves as the external clock input when running in this mode. the extclk input may also be used to clock some of the digital peripherals (e.g ., timers, pca, etc.) while sysclk runs fr om one of the internal oscillator sources. when not selected as the sysclk source, the extclk input is a lways re-synchronized to sysclk. clock control programmable divider: 1, 2, 4...128 sysclk low frequency 80 khz oscillator high frequency 24.5 mhz oscillator external clock input (extclk) to core and peripherals
c8051f85x/86x preliminary rev 0.6 119 clock sources and selection (hfosc0, lfosc0, and extclk) 16.4. clock selection the clksel register is used to select the clock source for the system. th e clksl field selects which oscillator source is used as the system clock, while clkdiv controls the programmable divider. clksl must be set to 01b for the system clock to run from the external oscillator; however the external osc illator may still clock certain peripherals (timers, pca) when the internal oscillator is sele cted as the system clock. in these cases, the external oscillator source is synchronized to the sysclk source. the system clock ma y be switched on-the-fly between any of the oscillator sources so long as the selected clock source is enabl ed and has settled, and clkdiv may be changed at any time. the internal high-fr equency and low-freq uency oscillators require little start- up time and may be selected as the system clock immediately following the re gister write which enables the oscilla tor. when selecting the extclk pin as a clock input source, the pin should be skipped in the crossbar and configured as a digital input. firmware should ensure that the external clock source is present or enable the missing clock detector before switching the clksl field.
c8051f85x/86x 120 preliminary rev 0.6 clock sources and selection (hfosc0, lfosc0, and extclk) 16.5. high frequency osci llator control registers register 16.1. oscicl: high frequency oscillator calibration bit 7 6 5 4 3 2 1 0 name oscicl typ e rw r e s e txxxxxxxx sfr address: 0xc7 table 16.1. oscicl register bit descriptions bit name function 7:0 oscicl oscillator calibration bits. these bits determine the intern al oscillator period. w h en se t to 00000000b, the oscillator operates at its fastest settin g. when set to 11111111b, the os cillator operates at its slow - est setting. the reset value is factory calib rated to generate an in ternal osc illator fre - quency of 24.5 mhz.
c8051f85x/86x preliminary rev 0.6 121 clock sources and selection (hfosc0, lfosc0, and extclk) 16.6. low frequency osci llator control registers register 16.2. osclcn: low frequency oscillator control bit 7 6 5 4 3 2 1 0 name osclen osclrdy osclf oscld typ e rw r rw rw r e s e t0 0xxxx0 0 sfr address: 0xb1 table 16.2. osclcn register bit descriptions bit name function 7 osclen internal l-f oscillator enable. this bit enables the internal low-frequency os cillato r . note that the low-frequency oscilla - tor is automatically enabled when the watchdog timer is active. 0: internal l-f oscillator disabled. 1: internal l-f oscillator enabled. 6 osclrdy internal l-f oscillator ready. 0: internal l-f oscillato r frequenc y not stabilized. 1: internal l-f oscilla tor frequenc y stabilized. 5:2 osclf internal l-f oscillator frequency control bits. fine-tune control bits for the internal l-f o scillator frequency . when set to 0000b, the l-f oscillator operates at its fastes t setting. when set to 1111b, the l-f oscillator operates at its slowest setting. the osclf bits should only be changed by firmware when the l-f oscillator is disabled (osclen = 0). 1:0 oscld internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected. note: osclrdy is only set back to 0 in the event of a device reset or a change to the oscld bits.
c8051f85x/86x 122 preliminary rev 0.6 clock sources and selection (hfosc0, lfosc0, and extclk) 16.7. clock selecti on control registers register 16.3. clksel: clock select bit 7 6 5 4 3 2 1 0 name reserved clkdiv reserved clksl typ e r rw r rw r e s e t00110000 sfr address: 0xa9 table 16.3. clksel register bit descriptions bit name function 7 reserved must write reset value. 6:4 clkdiv clock source divider. this field controls the divider applied to th e clock source s elected by clksl. the output of this divider is the system clock (sysclk). 000: sysclk is equal to selected clock source divided by 1. 001: sysclk is equal to selected clock source divided by 2. 010: sysclk is equal to selected clock source divided by 4. 011: sysclk is equal to select ed clock source divided by 8. 1 00: sysclk is equal to selected clock source divided by 16. 101: sysclk is equal to selected clock source divided by 32. 110: sysclk is equal to select ed clock source divided by 64. 1 11: sysclk is equal to selected clock source divided by 128. 3:2 reserved must write reset value. 1:0 clksl clock source select. selects the system clock source. 00: clock derived from the inte rnal high-frequency osc illator . 01: clock derived from the external oscillator circuit. 10: clock derived from the inte rnal low - frequency oscillator. 11: reserved.
c8051f85x/86x preliminary rev 0.6 123 comparators (cmp0 and cmp1) 17. comparators (cmp0 and cmp1) c8051f85x/86x devices include two on-chip programmable voltage comparators, cmp0 and cmp1. the two comparators are functionally identical, but have different c onnectivity within the device. a functional block diagram is shown in figure 17.1. figure 17.1. comparator functional block diagram 17.1. system connectivity comparator inputs are routed to port i/o pins or internal signals using the comparator mux registers. the comparators synchronous and asynchronous outputs can optionally be routed to port i/o pins through the port i/o crossbar. the output of either comparator may also be configured to generate a system interrupt. cmp0 may also be used as a reset source, or as a trigger to kill a pca output channel. the cmp0 inputs are selected in the cpt0mx register, while cpt1mx selects the cmp1 inputs. the cmxp field selects the comparators positive input (cpnp.x); the cmxn field selects the comparators negative input (cpnn.x). table 17.1 through table 17.4 detail the comparator input multiplexer options on the c8051f85x/86x family. see the port i/o crossbar sections for details on configuri ng comparator outputs via the digital crossbar. comparator inputs can be externally driven from C0.25 v to (v dd ) + 0.25 v without damage or upset. important note about comparator inputs: the port pins selected as comparator inputs should be configured as analog inputs in their associated port configuration re gister, and configured to be skipped by the crossbar. cmpn cpn+ cpn- programmable hysteresis programmable response time d q q cpn (synchronous) cpna (asynchronous) sysclk gnd port pins (8) negative input selection port pins (8) positive input selection internal ldo
c8051f85x/86x 124 preliminary rev 0.6 comparators (cmp0 and cmp1) table 17.1. cmp0 positive input multiplexer channels cmxp setting in register cpt0mx signal name qsop24 pin name qfn20 pin name soic16 pin name 0000 cp0p.0 p0.0 p0.0 p0.0 0001 cp0p.1 p0.1 p0.1 p0.1 0010 cp0p.2 p0.2 p0.2 p0.2 0011 cp0p.3 p0.3 p0.3 p0.3 0100 cp0p.4 p0.4 p0.4 p0.4 0101 cp0p.5 p0.5 p0.5 p0.5 0110 cp0p.6 p0.6 p0.6 reserved 0111 cp0p.7 p0.7 p0.7 reserved 1000 ldo internal 1.8 v ldo output 1001-1111 none no connection table 17.2. cmp0 negative input multiplexer channels cmxn setting in register cpt0mx signal name qsop24 pin name qfn20 pin name soic16 pin name 0000 cp0n.0 p0.0 p0.0 p0.0 0001 cp0n.1 p0.1 p0.1 p0.1 0010 cp0n.2 p0.2 p0.2 p0.2 0011 cp0n.3 p0.3 p0.3 p0.3 0100 cp0n.4 p0.4 p0.4 p0.4 0101 cp0n.5 p0.5 p0.5 p0.5 0110 cp0n.6 p0.6 p0.6 reserved 0111 cp0n.7 p0.7 p0.7 reserved 1000 gnd gnd 1001-1111 none no connection
c8051f85x/86x preliminary rev 0.6 125 comparators (cmp0 and cmp1) table 17.3. cmp1 positive input multiplexer channels cmxp setting in register cpt1mx signal name qsop24 pin name qfn20 pin name soic16 pin name 0000 cp1p.0 p1.0 p1.0 p0.6 0001 cp1p.1 p1.1 p1.1 p0.7 0010 cp1p.2 p1.2 p1.2 p1.0 0011 cp1p.3 p1.3 p1.3 p1.1 0100 cp1p.4 p1.4 p1.4 p1.2 0101 cp1p.5 p1.5 p1.5 p1.3 0110 cp1p.6 p1.6 p1.6 reserved 0111 cp1p.7 p1.7 reserved reserved 1000 ldo internal 1.8 v ldo output 1001-1111 none no connection table 17.4. cmp1 negative input multiplexer channels cmxn setting in register cpt1mx signal name qsop24 pin name qf n20 pin name so ic16 pin name 0000 cp1n.0 p1.0 p1.0 p0.6 0001 cp1n.1 p1.1 p1.1 p0.7 0010 cp1n.2 p1.2 p1.2 p1.0 0011 cp1n.3 p1.3 p1.3 p1.1 0100 cp1n.4 p1.4 p1.4 p1.2 0101 cp1n.5 p1.5 p1.5 p1.3 0110 cp1n.6 p1.6 p1.6 reserved 0111 cp1n.7 p1.7 reserved reserved 1000 gnd gnd 1001-1111 none no connection
c8051f85x/86x 126 preliminary rev 0.6 comparators (cmp0 and cmp1) 17.2. functional description the comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the po rt pins: a synchronous latched output (cpn), or an asynchronous raw output (cpna). the asynchronous cpna signal is available even when the system clock is not active. this allows the comparator to operate and generate an output with the device in stop mode. when disabled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the comparator is turned off. the comparator response time may be configured in software via the cptnmd register. selecting a longer response time reduces the comparator supply current. figure 17.2. comparator hysteresis plot the comparator hysteresis is software-programmable via its comparator control register cptncn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator hysteresis is programmable using the cphyn and cphyp fields in the comparator control register cptncn. the amount of negativ e hysteresis voltage is determined by the settings of the cphyn bits. as shown in figure 17.2, settings of 20, 10, or 5 mv (nomin al) of negative hysteresis can be programmed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cphyp bits. comparator interrupts can be generated on both rising-edge and falling-edge output transition s. the cpfif flag is set to logic 1 upon a comparator falling- edge occurrence, and the cp rif flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain se t until cleared by software. the comparator rising-edge interrupt mask is enabled by setting cprie to a logic 1. the comparator falling-edge interrupt mask is enabled by setting cpfie to a logic 1. the output state of the comparator can be obtained at an y time by reading the cpout bit. the comparator is enabled by setting the cpen bit to logic 1, an d is disabled by clearing this bit to logic 0. note that false rising edge s and falling edges can be detected when the comparator is first powered on or if changes are made to the hysteresis or response time cont rol bits. therefore, it is recommended that the rising- edge and falling-edge flags be ex plicitly cleared to logic 0 a short time af ter the comparator is enabled or its mode bits have been changed, before enabling comparator interrupts. cpn- positive programmable hysteresis (cphyp) cpn+ negative programmable hysteresis (cphyn) cp0 (out)
c8051f85x/86x preliminary rev 0.6 127 comparators (cmp0 and cmp1) 17.3. comparator control registers register 17.1. cpt0cn: comparator 0 control bit 7 6 5 4 3 2 1 0 name cpen cpout cprif cpfif c phyp cphyn type rw r rw rw rw rw r e s e t00000000 sfr address: 0x9b table 17.5. cpt0cn register bit descriptions bit name function 7 cpen comparator 0 enable bit. 0: comparator disabled. 1: comparator enabled. 6 cpout comparator 0 output state flag. 0: voltage on cp0p < cp0n. 1: voltage on cp0p > cp0n. 5 cprif comparator 0 rising-edge flag. must be cleared by software. 0: no comparator rising edge has occurr e d since this flag was last cleared. 1: comparator rising edge has occurred. 4 cpfif comparator 0 falling-edge flag. must be cleared by software. 0: no comparator falling-edge has occurr ed since this flag was last cleared. 1: comparator fallin g-edge has oc curred. 3:2 cph yp comparator 0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cphyn comparator 0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
c8051f85x/86x 128 preliminary rev 0.6 comparators (cmp0 and cmp1) register 17.2. cpt0md: comparator 0 mode bit 7 6 5 4 3 2 1 0 name cplout reserved cprie cpfie reserved cpmd ty pe rw r rw rw r rw r e s e t00000010 sfr address: 0x9d table 17.6. cpt0md register bit descriptions bit name function 7 cplout comparator 0 latched output flag. this bit represents the comparator output value at the most recent pca counter overflow. 0: comparator output was logic low at last pca overflow. 1: comparator output was logic high at last pca overflow. 6 reserved must write reset value. 5 cprie comparator 0 rising-edge interrupt enable. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. 4 cpfie comparator 0 falling-edge interrupt enable. 0: comparator falling-ed ge interrupt dis abled. 1: comparator falling-ed ge interrup t enabled. 3:2 reserved must write reset value. 1:0 cpmd comparator 0 mode select. these bits affect the response time and p ower consumption of the comparator. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f85x/86x preliminary rev 0.6 129 comparators (cmp0 and cmp1) register 17.3. cpt0mx: comparator 0 multiplexer selection bit 7 6 5 4 3 2 1 0 name cmxn cmxp ty pe rw rw r e s e t11111111 sfr address: 0x9f table 17.7. cpt0mx register bit descriptions bit name function 7:4 cmxn comparator 0 negative input mux selection. 0000: external pin cp0n.0 0001: external pin cp0n.1 0010: external pin cp0n.2 0011: external pin cp0n.3 0100: external pin cp0n.4 0101: external pin cp0n.5 0110: external pin cp0n.6 0111: external pin cp0n.7 1000: gnd 1001-1111: reserved. 3:0 cmxp comparator 0 positive input mux selection. 0000: external pin cp0p.0 0001: external pin cp0p.1 0010: external pin cp0p.2 0011: external pin cp0p.3 0100: external pin cp0p.4 0101: external pin cp0p.5 0110: external pin cp0p.6 0111: external pin cp0p.7 1000: internal ldo output 1001-1111: reserved.
c8051f85x/86x 130 preliminary rev 0.6 comparators (cmp0 and cmp1) register 17.4. cpt1cn: comparator 1 control bit 7 6 5 4 3 2 1 0 name cpen cpout cprif cpfif c phyp cphyn type rw r rw rw rw rw r e s e t00000000 sfr address: 0xbf table 17.8. cpt1cn register bit descriptions bit name function 7 cpen comparator 1 enable bit. 0: comparator disabled. 1: comparator enabled. 6 cpout comparator 1 output state flag. 0: voltage on cp1p < cp1n. 1: voltage on cp1p > cp1n. 5 cprif comparator 1 rising-edge flag. must be cleared by software. 0: no comparator rising edge has occurr e d since this flag was last cleared. 1: comparator rising edge has occurred. 4 cpfif comparator 1 falling-edge flag. must be cleared by software. 0: no comparator falling-edge has occurr ed since this flag was last cleared. 1: comparator fallin g-edge has oc curred. 3:2 cph yp comparator 1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cphyn comparator 1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
c8051f85x/86x preliminary rev 0.6 131 comparators (cmp0 and cmp1) register 17.5. cpt1md: comparator 1 mode bit 7 6 5 4 3 2 1 0 name cplout reserved cprie cpfie reserved cpmd ty pe rw r rw rw r rw r e s e t00000010 sfr address: 0xab table 17.9. cpt1md register bit descriptions bit name function 7 cplout comparator 1 latched output flag. this bit represents the comparator output value at the most recent pca counter overflow. 0: comparator output was logic low at last pca overflow. 1: comparator output was logic high at last pca overflow. 6 reserved must write reset value. 5 cprie comparator 1 rising-edge interrupt enable. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. 4 cpfie comparator 1 falling-edge interrupt enable. 0: comparator falling-ed ge interrupt dis abled. 1: comparator falling-ed ge interrup t enabled. 3:2 reserved must write reset value. 1:0 cpmd comparator 1 mode select. these bits affect the response time and p ower consumption of the comparator. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f85x/86x 132 preliminary rev 0.6 comparators (cmp0 and cmp1) register 17.6. cpt1mx: comparator 1 multiplexer selection bit 7 6 5 4 3 2 1 0 name cmxn cmxp ty pe rw rw r e s e t11111111 sfr address: 0xaa table 17.10. cpt1mx register bit descriptions bit name function 7:4 cmxn comparator 1 negative input mux selection. 0000: external pin cp1n.0 0001: external pin cp1n.1 0010: external pin cp1n.2 0011: external pin cp1n.3 0100: external pin cp1n.4 0101: external pin cp1n.5 0110: external pin cp1n.6 0111: external pin cp1n.7 1000: gnd 1001-1111: reserved. 3:0 cmxp comparator 1 positive input mux selection. 0000: external pin cp1p.0 0001: external pin cp1p.1 0010: external pin cp1p.2 0011: external pin cp1p.3 0100: external pin cp1p.4 0101: external pin cp1p.5 0110: external pin cp1p.6 0111: external pin cp1p.7 1000: internal ldo output 1001-1111: reserved.
c8051f85x/86x preliminary rev 0.6 133 cyclic redundancy check unit (crc0) 18. cyclic redundancy check unit (crc0) c8051f85x/86x devices include a cyclic redundancy che ck unit (crc0) that can perform a crc using a 16-bit polynomial. crc0 accepts a stream of 8-bi t data written to the crc0in register . crc0 posts the 16-bit result to an internal register. the internal resu lt register may be accessed indirect ly using the crcpnt bits and crc0dat register, as shown in figure 18.1. crc0 also has a bit reverse register fo r quick data manipulation. figure 18.1. crc0 block diagram 18.1. crc algorithm the crc unit generates a crc result equivalent to the following algorithm: 1. xor the input with the most-signifi cant bits of the current crc result. if this is the first iteration of the crc unit, the current crc result wi ll be the set initial value ? (0x0000 or 0xffff). 2a. if the msb of the crc result is set, shift the crc result and xor th e result with the selected polynomial. 2b. if the msb of the crc result is not set, shift the crc result. ? repeat steps 2a/2b for the number of input bits (8). the algorithm is also described in the following example. ? crc0 crc0dat crc0in byte-level bit reversal hardware crc calculation unit seed (0x0000 or 0xffff) automatic flash read control 8 8 8 8 8 flash memory crc0flip 8
c8051f85x/86x 134 preliminary rev 0.6 cyclic redundancy check unit (crc0) the 16-bit crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } // return the final remainder (crc value) return crc_acc; }? table 18.1 lists several input values and the a ssociated outputs using the 16-bit crc algorithm: table 18.1. example 16-bit crc outputs input output 0x63 0xbd35 0x8c 0xb1f4 0x7d 0x4eca 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166
c8051f85x/86x preliminary rev 0.6 135 cyclic redundancy check unit (crc0) 18.2. preparing fo r a crc calculation to prepare crc0 for a crc calculation, software should set the initial value of the resu lt. the polynomial used for the crc computation is 0x1021. the c rc0 result may be initialized to one of two values: 0x0000 or 0xffff. the following steps can be us ed to initialize crc0. 1. select the initial result value (set crcval to 0 for 0x0000 or 1 for 0xffff). 2. set the result to its initial value (write 1 to crcinit). 18.3. performing a crc calculation once crc0 is initialized, the input data stream is sequentially written to crc0in, one byte at a time. the crc0 result is automatically updated after eac h byte is written. the crc engine ma y also be configured to automatically perform a crc on one or more 256 byte blocks read from flash. the following steps can be used to automatically perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. write the index of the starting page to crc0auto. 3. set the autoen bit to 1 in crc0auto. 4. write the number of 256 byte blocks to perform in the crc calculation to crccnt. 5. write any value to crc0 cn (or or its contents with 0x00) to initiate the crc calculation. the cpu will not execute code any additional code until the crc operation completes. se e the note in the crc0cn register definition for more information on how to properly initiate a crc calculation. 6. clear the autoen bit in crc0auto. 7. read the crc result. 18.4. accessing th e crc0 result the internal crc0 result is 16 bits. the crcpnt bits sele ct the byte that is targeted by read and write operations on crc0dat and increment after each r ead or write. the calculation result will remain in the in ternal cr0 result register until it is set, ov erwritten, or additional data is written to crc0in. 18.5. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of each bit in a byte as shown in figure 18.2. each byte of data written to crc0flip is read back bit reversed. for example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathematical f unction used in algorithms such as the fft. figure 18.2. bit reversal crc0flip (write) crc0flip (read)
c8051f85x/86x 136 preliminary rev 0.6 cyclic redundancy check unit (crc0) 18.6. crc control registers register 18.1. crc0cn: crc0 control bit 7 6 5 4 3 2 1 0 name reserved crcinit crcval reserved crcpnt typ e r rw rw r rw r e s e t00010000 sfr address: 0xce table 18.2. crc0cn register bit descriptions bit name function 7:4 reserved must write reset value. 3 crcinit crc result initialization bit. writing a 1 to this bit initializes th e entire cr c res ult based on crcval. 2 crcval crc set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x0000 on write of 1 to crcinit. 1: crc result is set to 0xffff on write of 1 to c rcinit. 1 reserved must write reset value. 0 crcpnt crc result pointer. specifies the byte of the crc result to be read/w ritten on the ne xt access to crc0dat. this bit will automatically togg le upon each read or write. 0: crc0dat accesses bits 7- 0 of the 16-bit crc result. 1: crc0dat accesses bits 15-8 of the 16-bit crc result. note: upon initiation of an auto matic crc calculation, the th ree cycles following a write to crc0cn that initiate a crc operation must only co ntain instructions which execute in the same number of cycles as the number of bytes in the instruction. an example of such an in struction is a 3-byte mov that targets the crc0flip register. when programming in c, the dummy value written to crc0flip should be a non -zero value to prevent the co mpiler from generating a 2- byte mov instruction.
c8051f85x/86x preliminary rev 0.6 137 cyclic redundancy check unit (crc0) register 18.2. crc0in: crc0 data input bit 7 6 5 4 3 2 1 0 name crc0in typ e rw r e s e t00000000 sfr address: 0xdd table 18.3. crc0in register bit descriptions bit name function 7:0 crc0in crc data input. each write to crcin results in th e written da ta being computed into the existing crc result according to the crc algorithm.
c8051f85x/86x 138 preliminary rev 0.6 cyclic redundancy check unit (crc0) register 18.3. crc0dat: crc0 data output bit 7 6 5 4 3 2 1 0 name crc0dat typ e rw r e s e t00000000 sfr address: 0xde table 18.4. crc0dat register bit descriptions bit name function 7:0 crc0dat crc data output. each read or write performed on crc0dat targ et s the crc result bits pointed to by the crc0 result pointer (crc0pnt bits in crc0cn). note: crc0dat may not be valid for one cycle after setting the crc0init bit in the crc0cn register to 1. any time crc0init is written to 1 by firmware, at least one instruction should be performed before reading crc0dat.
c8051f85x/86x preliminary rev 0.6 139 cyclic redundancy check unit (crc0) register 18.4. crc0auto: crc0 automatic control bit 7 6 5 4 3 2 1 0 name autoen reserved crcst typ e rw r rw r e s e t00000000 sfr address: 0xd2 table 18.5. crc0auto register bit descriptions bit name function 7 autoen automatic crc calc ulation enable. when autoen is set to 1, any write to c rc0cn will initiate an automatic crc starting at flash sector crcst and continuing for crccnt sectors. 6 reserved must write reset value. 5:0 crcst automatic crc ca lculation s t arting block. these bits specify the flash block to star t the automatic crc calculation. the starting address of the first flash bl ock included in the automa tic crc calculation is crcst x block_size, where block_size is 256 bytes.
c8051f85x/86x 140 preliminary rev 0.6 cyclic redundancy check unit (crc0) register 18.5. crc0cnt: crc0 automatic flash sector count bit 7 6 5 4 3 2 1 0 name crcdn reserved crccnt typ e r r rw r e s e t10000000 sfr address: 0xd3 table 18.6. crc0cnt register bit descriptions bit name function 7 crcdn automatic crc calcul ation complete. set to 0 when a crc calculation is in progre ss. co de execution is stopped during a crc calculation; therefore, reads fr om firmware will always return 1. 6:5 reserved must write reset value. 4:0 crccnt automatic crc calcul ation block count. these bits specify the number of fla s h blocks to include in an automatic crc calculation. the last address of the last flash block in cluded in the automatic crc calculation is (crcst+crccnt) x block size - 1. the block size is 256 bytes.
c8051f85x/86x preliminary rev 0.6 141 cyclic redundancy check unit (crc0) register 18.6. crc0flip: crc0 bit flip bit 7 6 5 4 3 2 1 0 name crc0flip typ e rw r e s e t00000000 sfr address: 0xcf table 18.7. crc0flip register bit descriptions bit name function 7:0 crc0flip crc0 bit flip. any byte written to crc0flip is read back in a bit-r e versed order, i.e., the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the data read back will be 0x03. if 0x05 is written to crc0flip, the dat a read back will be 0xa0.
c8051f85x/86x 142 preliminary rev 0.6 external interrupts (int0 and int1) 19. external interrupts ( int0 and int1) the c8051f85x/86x device family includes two external digital interrupt sources (int0 and int1 ), with dedicated interrupt sources (up to 16 additional i/o interrupts are available through the port match function). as is the case on a standard 8051 architecture, certain controls for these two interrupt sources are available in the timer0/1 registers. extensions to these controls which provid e additional functionality on c8051f85x/86x devices are available in the it01cf register. int0 and int1 are configurable as active high or low, edge or level sensitive. the in0pl and in1pl bits in the it01cf register select active hi gh or active low; the it0 and it1 bits in tcon select level or edge sensitive. the table belo w lists the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register. note that int0 and int1 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins without disturbing the peripheral that wa s assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). ie0 and ie1 in the tcon register serve as the interrupt-pendin g flags for the int0 and int1 external interrupts, respectively. if an int0 or int1 external interrupt is configured as e dge-sensitive, the corresponding interrupt- pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); the flag remains logic 0 while the input is inactive. the ex ternal interrup t source must hold the input active until the interrupt request is recogni zed. it must then deactivate the interrupt request before execution of the isr completes or anot her interrupt request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 active high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive
c8051f85x/86x preliminary rev 0.6 143 external interrupt s (int0 and int1) 19.1. external interrupt control registers register 19.1. it01cf: int0/int1 configuration bit 7 6 5 4 3 2 1 0 name in1pl in1sl in0pl in0sl ty pe rw rw rw rw r e s e t00000001 sfr address: 0xe4 table 19.1. it01cf register bit descriptions bit name function 7 in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl int1 port pin selection bits. these bits select which port pin is assigned to int1. this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin with out disturbing the peripheral that has been assigned the port pin via t he crossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3 in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl int0 port pin selection bits. these bits select which port pin is assigned to int0. this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin with out disturbing the peripheral that has been assigned the port pin via t he crossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7
c8051f85x/86x 144 preliminary rev 0.6 external interrupts (int0 and int1)
c8051f85x/86x 146 preliminary rev 0.6 programmable counter array (pca0) 20. programmable counter array (pca0) the programmable counter array (pca0) provides three ch annels of enhanced timer and pwm functionality while requiring less cpu intervention than standard counter/timers. the pca consis ts of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. the counter /timer is driven by a programmable timebase that can select between seven sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, low frequency oscillator divide d by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compar e module may be configured to operate independently in one of six modes: edge-triggered ca pture, software timer, high-speed ou tput, frequency output, 8 to 11-bit pwm, or 16-bit pwm. additionally, all pwm modes suppor t both center and edge-aligned operation. the external oscillator and lfo oscillator clock options allow the pca to be clocked by an external oscillator or the lfo while the internal oscillator drives the sys tem clock. each capture/compare modu le has its own associated i/o line (cexn) which is routed through the crossbar to port i/o wh en enabled. the i/o signals have programmable polarity and comparator 0 c an optionally be used to perform a cycle-by-cycle kill operatio n on the pca outputs. a pca block diagram is shown in figure 20.1 figure 20.1. pca0 block diagram channel 2 mode control capture / compare channel 1 mode control capture / compare pca0 eci cex0 extclk / 8 l-f oscillator / 8 timer 0 overflow sysclk sysclk / 4 sysclk / 12 polarity select control / configuration comparator clear enable output drive logic pca counter channel 0 mode control capture / compare cex1 cex2 comparator 0 output interrupt logic sync sync sync sysclk
c8051f85x/86x preliminary rev 0.6 147 programmable co unter array (pca0) 20.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bit sfrs: pca0l and pca0h. pca0h is the high byte of the 16-bit counter/timer and pca0l is the low byte. reading pca0 l automatically latches th e value of pca0h into a snapshot register; the following pca0h read accesses this snapshot register. reading the pca0l register first guarantees an accurate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 C cps0 bits in the pca0md register select the timebase for the counter/ timer as shown in table 20.1. when the counter/timer overflows from 0xffff to 0x0000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. clearing the cidl bit in the pca0md register allows the pca to continue no rmal operation while the cpu is in idle mode. 20.2. pca0 interrupt sources the pca0 module shares one interrupt vector among all of its modules. there are are several event flags that can be used to generate a pca0 interrupt. they are: the ma in pca counter overflow flag (cf), which is set upon a 16- bit overflow of the pca0 counter, an intermediate overflow flag (covf), which can be set on an overflow from the 8th - 11th bit of the pca0 counter, and the individual flags for each pca channel (ccfn), which are set according to the operation mode of that module. these event flags ar e always set when the trigger condition occurs. each of these flags can be individually selected to generate a pc a0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pc a0 interrupts must be globally enabled before any individual interrupt sources are recognized by the proce ssor. pca0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. table 20.1. pca timebase input options cps2 cps1 cps0 timebase 000 system clock divided by 12 001 system clock divided by 4 010 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) * 100 system clock 101 external oscillator s ource divided by 8 * 110 low frequency oscillator divided by 8 * 111 reserved note: synchronized with the system clock.
c8051f85x/86x 148 preliminary rev 0.6 programmable counter array (pca0) 20.3. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high-speed output, frequency output, 8 to 11-bit pulse width modulato r, or 16-bit pulse width modulator. table 20.2 summa rizes the bit settings in th e pca0cpmn and pca0pwm registers used to select the pca capture/compare modules operatin g mode. note that all modules set to use 8, 9, 10 or 11-bit pwm mode must use the same cycle length (8C11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. 20.3.1. output polarity the output polarity of each pca channel is individually s e lectable using the pca0pol register. by default, all output channels are configured to drive the pca output signals (cexn) with their internal polarity. when the cexnpol bit for a specific channel is set to 1, that cha nnels output signal will be inverted at the pin. all other properties of the channel are unaffected, and the inversio n does not apply to pca input signals. note that changes in the pca0pol register take effect immediately at the associated output pin. table 20.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number 7 6 5 4 3 2 1 0 7 6 5 4C3 2C0 capture triggered by positive edge on cexn x x 1 0 0 0 0 a 0 x b xx xxx capture triggered by negative edge on cexn x x 0 1 0 0 0 a 0 x b xx xxx capture triggered by any transition on cexn x x 1 1 0 0 0 a 0 x b xx xxx software timer x c 0 0 1 0 0 a 0 x b xx xxx high speed output x c 0 0 1 1 0 a 0 x b xx xxx frequency output x c 0 0 0 1 1 a 0 x b xx xxx 8-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a 0 x b xx 000 9-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xx 001 10-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xx 010 11-bit pulse width modulator ( note 7 ) 0 c 0 0 e 0 1 a d x b xx 011 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xx xxx notes: 1. x = dont care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th - 11th bit overflow interr upt (depends on setting of clsel). 4. c = when set to 0, the digital comparator is off. for high sp eed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, th is generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pc a0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pwm mode use the same cycle length setting.
c8051f85x/86x preliminary rev 0.6 149 programmable co unter array (pca0) 20.3.2. edge-triggered capture mode in this mode, a valid transition on th e cexn pin causes the pca to capture the value of the pca counter/timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transition that triggers the capture: low-to- high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interr upt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. if both cappn and capnn bits are set to logic 1, then the state of th e port pin associated with cexn can be read directly to determine whether a rising-edge or fallin g-edge caused the capture. figure 20.2. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be re cognized by the hardware. cexn pca0l pca0cpln pca0h pca0cphn cappn capnn ccfn (interrupt flag) pca clock capture
c8051f85x/86x 150 preliminary rev 0.6 programmable counter array (pca0) 20.3.3. software timer (compare) mode in software timer mode, the pca counte r/timer valu e is compared to the modu le's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn in terrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln cl ears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 20.3. pca software timer mode diagram pca0l pca0cpln pca0h pca0cphn ecomn (compare enable) pca clock 16-bit comparator match ccfn (interrupt flag) matn (match enable)
c8051f85x/86x preliminary rev 0.6 151 programmable co unter array (pca0) 20.3.4. high-speed output mode in high-speed output mode, a modules associated cexn pin is tog gled each time a match occurs between the pca counter and the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is en abled. the ccfn bit is not automatica lly cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bits in the pca0cpmn register enab les the high-speed ou tput mode. if ecomn is cl eared, the associated pin will retain its state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln cl ears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 20.4. pca high-speed output mode diagram pca0l pca0cpln pca0h pca0cphn ecomn (compare enable) pca clock 16-bit comparator match ccfn (interrupt flag) matn (match enable) toggle togn (toggle enable) cexn
c8051f85x/86x 152 preliminary rev 0.6 programmable counter array (pca0) 20.3.5. frequency output mode frequency output mode produces a programmable-frequency sq ua re wave on the modules associated cexn pin. the capture/compare module high byte holds the number of pca clocks to co unt before the output is toggled. the frequency of the square wave is then defined by equation 20.1. equation 20.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 C 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is compared to the pca counter low byte; on a match, n is toggled and the offset held in the high byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn register. note that the matn bit should normally be set to 0 in this mode. if the matn bi t is set to 1, the ccfn flag for the ch annel will be set when the 16-bit pca0 counter and the 16-bit capture/compare register for the channel are equal. figure 20.5. pca frequency output mode f cexn f pca 2 pca0 cphn ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. pca0l ecomn (compare enable) pca clock 8-bit comparator match toggle togn (toggle enable) cexn 8-bit adder adder enable pca0cpln pca0cphn
c8051f85x/86x preliminary rev 0.6 153 programmable co unter array (pca0) 20.4. pwm waveform generation the pca can generate edge or center-aligned pwm waveforms with resolutions of 8, 9, 10, 11 or 16 bits. pwm resolution depends on the module setup, as sepcified wit hin the individual module pca0cpmn registers as well as the pca0pwm register. modules can be configured for 8-11 bit mode, or for 16-bit mode individually using the pca0cpmn registers. all modules conf igured for 8-11 bit mode will have t he same resolution, specified by the pca0pwm register. when operating in one of the pwm mo des, each module may be individually configured for center or edge-aligned pwm waveforms. each channel ha s a single bit in the pca0cent register to select between the two options. 20.4.1. edge aligned pwm when configured for edge-a ligned mode, a mo dul e will generate an ed ge transition at two points for every 2 n pca clock cycles, where n is the selected pw m resolution in bits. in edge-aligned mode, these two edges are referred to as the match and overflow edges. the polarity at the output pin is selectable, and can be inverted by setting the appropriate channel bit to 1 in the pca0pol register. prior to inversion, a match edge sets the channel to logic high, and an overflow edge clears the channel to logic low. the match edge occurs when the the lowest n bits of the modules pca0cpn register match the corresponding bits of the main pca0 counte r register. for example, with 10-bit pwm, the ma tch edge will occur any time bits 9-0 of the pca0cpn register match bits 9-0 of the pca0 counter value. the overflow edge occurs when an over flow of the pca0 counter happens at the desired resolution. for example, with 10-bit pwm, the overflow edge will occu r when bits 0-9 of the pca0 counter tr ansition from all 1s to all 0s. all modules configured for ed ge-aligned mode at th e same resolution will align on the overflow edge of the waveforms. an example of the pwm timing in edge-aligned mode for two channels is shown in figure 20.6. in this example, the cex0pol and cex1pol bits are cleared to 0. figure 20.6. edge-aligned pwm timing for a given pca resolution, the unused high bits in t he pca0 counter and the pca0cpn compare registers are ignored, and only the used bits of the pca0cpn register determine the duty cycle. equation 20.2 describes the duty cycle when cexnpol in th e pca0pol regsiter is cleared to 0. equat ion 20.3 describes th e duty cycle when cexnpol in the pca0pol regsiter is set to 1. a 0% duty cycle for the ch annel (with cexnpol = 0) is achieved by 0xffff 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 counter (pca0) 0x0001 capture / compare (pca0cp0) output (cex0) pca clock match edge overflow edge 0x0005 capture / compare (pca0cp1) output (cex1) match edge
c8051f85x/86x 154 preliminary rev 0.6 programmable counter array (pca0) clearing the modules ecom bit to 0. this will disable the comparison, and prevent the match ed ge from occuring. note that although the pca0cpn compare register determin es the duty cycle, it is not always appropriate for firmware to update this register directly. see the sections on 8 to 11-bit and 16-bit pwm mode for additional details on adjusting duty cycle in the various modes. equation 20.2. n-bit edge-aligned pwm duty cycle with cexnpol = 0 (n = pwm resolution) equation 20.3. n-bit edge-aligned pwm duty cycle with cexnpol = 0 (n = pwm resolution) duty cycle 2 n pca0cpn C ?? 2 n ----------------------------------------- - = duty cycle pca0cpn 2 n ------------------------ - =
c8051f85x/86x preliminary rev 0.6 155 programmable co unter array (pca0) 20.4.2. center aligned pwm when configured for center-aligned mo de, a module will generate an edge transition at two points for every 2 (n+1) pca clock cycles, where n is the selected pwm resolution in bits. in cent er-aligned mode, these two edges are referred to as the up and down edges. the polarity at th e output pin is selectable, and can be inverted by setting the appropriate channel bit to 1 in the pca0pol register. the generated waveforms are centered about the points where the lower n bits of the pca0 counter are zero. the (n+1) th bit in the pca0 counter acts as a selection between up and down edges. in 16-bit mode, a special 17th bit is implemented internally for this purpose. at the center point, the (non-inverted) channel output will be low when the (n+1) th bit is 0 and high when the (n+1) th bit is 1, except for cases of 0% and 100% duty cycle. prior to inversion, an up edge sets the channel to logic hi gh, and a down edge clears the channel to logic low. down edges occur when the (n+1) th bit in the pca0 counter is one, and a logical inversion of the value in the modules pca0cpn register matches t he main pca0 counter register for the lowest n bits. for example, with 10- bit pwm, the down edge will occur when t he ones complement of bits 9-0 of the pca0cpn register match bits 9-0 of the pca0 counter, and bit 10 of the pca0 counter is 1. up edges occur when the (n+1) th bit in the pca0 counter is zero, and the lowest n bits of the modules pca0cpn register match the value of (pca0 - 1). for example, wit h 10-bit pwm, the up edge will o ccur when bits 9-0 of the pca0cpn register are one less than bits 9-0 of the pc a0 counter, and bit 10 of the pca0 counter is 0. an example of the pwm timing in center-aligned mode for tw o channels is shown in figure 20.7. in this example, the cex0pol and cex1pol bits are cleared to 0. figure 20.7. center-aligned pwm timing equation 20.4 describes the duty cycle when cexnpol in the pca0pol regsiter is cleared to 0. equation 20.5 describes the duty cycle when cexnpol in the pca0pol regsiter is set to 1. the equations are true only when the lowest n bits of the pca0cpn register are not all 0s or all 1s. with cexnpol equa l to zero, 100% duty cycle is produced when the lowest n bits of pca0cpn are all 0, and 0% duty cycle is produced when the lowest n bits of pca0cpn are all 1. for a given pca resolution, the unu sed high bits in the pca0 counter and the pca0cpn compare registers are ignored, and on ly the used bits of the pca0cp n register determine the duty cycle. 0xfb 0xfc 0xfd 0xfe 0xff 0x00 0x01 0x02 0x03 0x04 counter (pca0l) 0x01 capture / compare (pca0cpl0) output (cex0) pca clock down edge 0x04 capture / compare (pca0cpl1) output (cex1) up edge down edge up edge center center center
c8051f85x/86x 156 preliminary rev 0.6 programmable counter array (pca0) note that although the pca0cpn compare register determin es the duty cycle, it is not always appropriate for firmware to update this register directly. see the sections on 8 to 11-bit and 16-bit pwm mode for additional details on adjusting duty cycle in the various modes. equation 20.4. n-bit center-aligned pwm duty cycle wi th ce xnpol = 0 (n = pwm resolution) equation 20.5. n-bit center-aligned pwm duty cycle wi th ce xnpol = 1 (n = pwm resolution) duty cycle 2 n pca0cpn C ?? 1 2 -- - C 2 n -------------------------------------------------- - = duty cycle pca0cpn 1 2 -- - + 2 n ---------------------------------- =
c8051f85x/86x preliminary rev 0.6 157 programmable co unter array (pca0) 20.4.3. 8 to11-bit pulse width modulator modes each module can be used independently to generate a pu lse w idth modulated (pwm) output on its associated cexn pin. the frequency of the output is dependent on th e timebase for the pca counter/timer, and the setting of the pwm cycle length (8 through 11-bits). for backwards-compat ibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly different than 9 through 11-bit pwm modes. it is important to note that all channels config ured for 8 to 11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11-bit m ode (for example). however, other pca channels can be configured to pin capture, high-speed output, softwa re timer, frequency output, or 16-bit pwm mode independently. each channel configured for a pwm mode c an be individually selected to operate in edge-aligned or center-aligned mode. 20.4.3.1. 8-bit pulse width modulator mode in 8-bit pwm mode, the duty cycle is determined by the value of the low byte of the pca0cpn register (pca0cpln). to adjust the duty cycle, pca0cpln shou ld not normally be written directly. instead, it is recommended to adjust the duty cycle using the high byte of the pca0cpn register (register pca0cphn). this allows seamless updating of the pwm waveform, as pca0cp ln is reloaded automatically with the value stored in pca0cphn during the overflow edge (in edge-aligned mode) or the up edge (in center-aligned mode). setting the ecomn and pwmn bits in the pca0cpmn regi ster, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulato r mode. if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occu r every 256 pca clock cycles. 20.4.3.2. 9 to 11-bit pulse width modulator mode in 9 to 11-bit pwm mode, the duty cycle is determined by the value of the least significant n bits of the pca0cpn register, where n is the selected pwm resolution. to adjust the duty cycle, pca0cpn should not normally be wr itten directly. instead, it is recommended to adjust the duty cycle by writing to an auto- reload register, which is dual-mapped into the pca0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-justified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. this allows seamless updating of the pwm waveform, as the pca0cpn register is reloaded automatically with the value stored in the auto-reload r egisters during the overflow edge (in edge-aligned mode) or the up edge (in center-aligned mode). setting the ecomn and pwmn bits in the pca0cpmn regi ster, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulato r mode. if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the covf flag in pca0pwm can be used to detect the overflow or down edge. the 9 to 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn flag for the module will be set each time a match edge or up edge occurs. the covf flag in pca0pwm can be used to detect the overflow or down edge. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be written first. writing to pca0cpln cl ears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1.
c8051f85x/86x 158 preliminary rev 0.6 programmable counter array (pca0) 20.4.4. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mo de. 1 6-bit pwm mode is independent of the other (8 through 11-bit) pwm modes. the entire pca0cp register is used to determine the duty cycle in 16-bit pwm mode. to output a varying duty cycle, new value writes should be synchronized with the pca ccfn match flag to ensure seamless updates. 16-bit pwm mode is enabled by setting the ecomn, pw mn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, the match interrupt flag should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compar e register writes. if the matn bit is set to 1, the ccfn flag for the modul e will be set each time a match edge or up edge occurs. the cf flag in pca0cn can be used to detect the overflow or down edge. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln cl ears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1.
c8051f85x/86x preliminary rev 0.6 159 programmable co unter array (pca0) 20.5. comparator clear function in 8/9/10/11/16-bit pwm mode s, the comparator cl ear function utilizes the comparat or0 output synchronized to the system clock to clear cexn to logic lo w for the current pwm cycle. this comparator clear function can be enabled for each pwm channel by setting the cpcen bits to 1 in the pca0clr sfr. when the comparator clear function is disabled, cexn is unaffected. the asynchronous comparator 0 output is logic high when the voltage of cp0+ is greater than cp0- and logic low when the voltage of cp0+ is less than cp0-. the polarity of the comparator 0 output is used to clear cexn as follows: when cpcpol = 0, cexn is cleared on the fa lling edge of the comparator0 output (see figure 20.8); when cpcpol = 1, cexn is cleared on the rising edge of the compartor0 output (see figure 20.9). figure 20.8. cexn with cpcen = 1, cpcpol = 0 figure 20.9. cexn with cpcen = 1, cpcpol = 1 in the pwm cycle following the current cycle, should the comparator 0 output remain logic low when cpcpol = 0 or logic high when cpcpol = 1, cexn will continue to be cleared. see figu re 20.10 and figure 20.11. figure 20.10. cexn with cpcen = 1, cpcpol = 0 figure 20.11. cexn with cpcen = 1, cpcpol = 1 cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 0) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 1) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 0) cexn (cpcen = 0) cexn (cpcen = 1) comparator0 output (cpcpol = 1)
c8051f85x/86x 160 preliminary rev 0.6 programmable counter array (pca0) 20.6. pca control registers register 20.1. pca0cn: pca control bit 7 6 5 4 3 2 1 0 name cf cr reserved ccf2 ccf1 ccf0 ty pe rw rw r rw rw rw r e s e t00000000 sfr address: 0xd8 (bit-addressable) table 20.3. pca0cn register bit descriptions bit name function 7 cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when th e co unter/timer overflow (cf) interrupt is enabled, settin g this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hard - ware and must be cleared by software. 6 cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:3 reserved must write reset value. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capt ure occ urs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capt ure occ urs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capt ure occ urs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software.
c8051f85x/86x preliminary rev 0.6 161 programmable co unter array (pca0) register 20.2. pca0md: pca mode bit 7 6 5 4 3 2 1 0 name cidl reserved cps ecf typ e rw r rw rw r e s e t00000000 sfr address: 0xd9 table 20.4. pca0md register bit descriptions bit name function 7 cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the s ystem controller is in idle mode. 1: pca operation is suspended while th e system contr o ller is in idle mode. 6:4 reserved must write reset value. 3:1 cps pca counter/time r pu ls e select. these bits select the timebase source for the pca counter. 000: system clock divided by 12. 001: system clock divided by 4. 010: timer 0 overflow. 011: high-to-low transitions on eci (m ax rate = system cl ock divided by 4). 100: system clock. 101: external clock divided by 8 (s y n chronized with the system clock). 110: low frequency os cillator divided by 8. 111: reserved. 0 ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co un te r/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set.
c8051f85x/86x 162 preliminary rev 0.6 programmable counter array (pca0) register 20.3. pca0pwm: pca pwm configuration bit 7 6 5 4 3 2 1 0 name arsel ecov covf reserved clsel ty pe rw rw rw r rw r e s e t00000000 sfr address: 0xf7 table 20.5. pca0pwm register bit descriptions bit name function 7 arsel auto-reload register select. this bit selects whether to read and write th e no rmal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9 to 11 -bit pwm modes. in all other modes, the auto- reload registers have no function. 0: read/write capture/compare regi ster s at pca0 cphn and pca0cpln. 1: read/write auto-reload registers at pca0cphn and pca0cpln. 6 ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not genera te pc a interrupt s. 1: a pca interrupt will be g enerated when cov f is set. 5 covf cycle overflow flag. this bit indicates an overflow of the 8th to 1 1 th bit of the main pca counter (pca0). the specific bit used for this flag depends on t he setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by software. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:3 reserved must write reset value. 2:0 clsel cycle length select. when 16-bit pwm mode is not selected, these bit s select the length of the pwm cycle. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels configured to16-bit pwm mode. 000: 8 bits. 001: 9 bits. 010: 10 bits. 011: 11 bits. 100-111: reserved.
c8051f85x/86x preliminary rev 0.6 163 programmable co unter array (pca0) register 20.4. pca0clr: pca comparator clear control bit 7 6 5 4 3 2 1 0 name cpcpol reserved cpce2 cpce1 cpce0 ty perw r rwrwrw r e s e t00000000 sfr address: 0x9c table 20.6. pca0clr register bit descriptions bit name function 7 cpcpol comparator clear polarity. selects the polarity of the c o mparator result that w ill clear the pca channel(s). 0: pca channel(s) will be cleared when comp arator res ult goes logic low. 1: pca channel(s) will be cleared when co mp arator res ult goes logic high. 6:3 reserved must write reset value. 2 cpce2 comparator clear enable for cex2. enables the comparator clear function on pca channel 2. 1 cpce1 comparator clear enable for cex1. enables the comparator clear function on pca channel 1. 0 cpce0 comparator clear enable for cex0. enables the comparator clear function on pca channel 0.
c8051f85x/86x 164 preliminary rev 0.6 programmable counter array (pca0) register 20.5. pca0cpm0: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16 ecom capp capn mat tog pwm eccf ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xda table 20.7. pca0cpm0 register bit descriptions bit name function 7 pwm16 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecom comparator function enable. this bit enables the comparator function. 5 capp capture positive function enable. this bit enables the positive edge capture capability. 4 capn capture negative function enable. this bit enables the negative edge capture capability. 3 mat match function enable. this bit enables the match function. when en ab led, matche s of the pca counter with a module's capture/compare regist er cause the ccf0 bit in the pca0md register to be set to logic 1. 2 tog toggle function enable. this bit enables the toggle function. when en able d, matches of the pca counter with the capture/compare register cause the logic leve l on the cex0 pin to toggle. if the pwm bit is also set to logic 1, the module operates in frequency output mode. 1 pwm pulse width modulation mode enable. this bit enables the pwm function. when enabled, a pulse width modulated signal is out - put on the cex0 pin. 8 to 11-bit pwm is used if pwm16 is cleared; 16-bit mode is used if pwm16 is set to logic 1. if the tog bit is also set, the module operates in frequency output mode. 0 eccf capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccf0) interrupt. 0: disable ccf0 interrupts. 1: enable a capture/compare flag interrupt request when ccf0 is set.
c8051f85x/86x preliminary rev 0.6 165 programmable co unter array (pca0) register 20.6. pca0l: pca counter/timer low byte bit 7 6 5 4 3 2 1 0 name pca0l typ e rw r e s e t00000000 sfr address: 0xf9 table 20.8. pca0l register bit descriptions bit name function 7:0 pca0l pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer.
c8051f85x/86x 166 preliminary rev 0.6 programmable counter array (pca0) register 20.7. pca0h: pca counter/timer high byte bit 7 6 5 4 3 2 1 0 name pca0h typ e rw r e s e t00000000 sfr address: 0xfa table 20.9. pca0h register bit descriptions bit name function 7:0 pca0h pca counter/timer high byte. the pca0h register holds the high byte (msb ) of the 16-bit pca counter/timer. reads of this register will read the c ontents of a snapshot register , whose contents are updated only when the contents of pca0l are read.
c8051f85x/86x preliminary rev 0.6 167 programmable co unter array (pca0) register 20.8. pca0cpl0: pca capture module low byte bit 7 6 5 4 3 2 1 0 name pca0cpl0 typ e rw r e s e t00000000 sfr address: 0xfb table 20.10. pca0cpl0 register bit descriptions bit name function 7:0 pca0cpl0 pca capture module low byte. the pca0cpl0 register holds the low byte (lsb) of the 16-bit capture module.this reg - ister address also allows access to the low byte of the corresponding pca channels a u to-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will clear the modules ecom bit to a 0.
c8051f85x/86x 168 preliminary rev 0.6 programmable counter array (pca0) register 20.9. pca0cph0: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cph0 typ e rw r e s e t00000000 sfr address: 0xfc table 20.11. pca0cph0 register bit descriptions bit name function 7:0 pca0cph0 pca capture module high byte. the pca0cph0 register holds the high byte (m sb) of the 16-bit capture module.this register address also allows access to the high byte of the corresponding pca channels auto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will set the modules ecom bit to a 1.
c8051f85x/86x preliminary rev 0.6 169 programmable co unter array (pca0) register 20.10. pca0pol: pca output polarity bit 7 6 5 4 3 2 1 0 name reserved cex2pol cex1pol cex0pol ty pe r rwrwrw r e s e t00000000 sfr address: 0x96 table 20.12. pca0pol register bit descriptions bit name function 7:3 reserved must write reset value. 2 cex2pol cex2 output polarity. selects the polarity of the cex2 output channe l. when this bit is modified, the change takes effect at the pin immediately. 0: use default polarity. 1: invert polarity. 1 cex1pol cex1 output polarity. selects the polarity of the cex1 output channe l. when this bit is modified, the change takes effect at the pin immediately. 0: use default polarity. 1: invert polarity. 0 cex0pol cex0 output polarity. selects the polarity of the cex0 output channe l. when this bit is modified, the change takes effect at the pin immediately. 0: use default polarity. 1: invert polarity.
c8051f85x/86x 170 preliminary rev 0.6 programmable counter array (pca0) register 20.11. pca0cent: pca center alignment enable bit 7 6 5 4 3 2 1 0 name reserved cex2cen cex1cen cex0cen ty pe r rwrwrw r e s e t00000000 sfr address: 0x9e table 20.13. pca0cent register bit descriptions bit name function 7:3 reserved must write reset value. 2 cex2cen cex2 center alignment enable. selects the alignment properties of the cex2 ou tp ut channel when operated in any of the pwm modes. this bit does not affe ct the operation of non-pwm modes. 0: edge-aligned. 1: center-aligned. 1 cex1cen cex1 center alignment enable. selects the alignment properties of the cex1 ou tp ut channel when operated in any of the pwm modes. this bit does not affe ct the operation of non-pwm modes. 0: edge-aligned. 1: center-aligned. 0 cex0cen cex0 center alignment enable. selects the alignment properties of the cex0 ou tp ut channel when operated in any of the pwm modes. this bit does not affe ct the operation of non-pwm modes. 0: edge-aligned. 1: center-aligned.
c8051f85x/86x preliminary rev 0.6 171 programmable co unter array (pca0) register 20.12. pca0cpm1: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16 ecom capp capn mat tog pwm eccf ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xdb table 20.14. pca0cpm1 register bit descriptions bit name function 7 pwm16 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecom comparator function enable. this bit enables the comparator function. 5 capp capture positive function enable. this bit enables the positive edge capture capability. 4 capn capture negative function enable. this bit enables the negative edge capture capability. 3 mat match function enable. this bit enables the match function. when en ab led, matche s of the pca counter with a module's capture/compare regist er cause the ccf1 bit in the pca0md register to be set to logic 1. 2 tog toggle function enable. this bit enables the toggle function. when en able d, matches of the pca counter with the capture/compare register cause the logic leve l on the cex1 pin to toggle. if the pwm bit is also set to logic 1, the module operates in frequency output mode. 1 pwm pulse width modulation mode enable. this bit enables the pwm function. when enabled, a pulse width modulated signal is out - put on the cex1 pin. 8 to 11-bit pwm is used if pwm16 is cleared; 16-bit mode is used if pwm16 is set to logic 1. if the tog bit is also set, the module operates in frequency output mode. 0 eccf capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccf1) interrupt. 0: disable ccf1 interrupts. 1: enable a capture/compare flag interrupt request when ccf1 is set.
c8051f85x/86x 172 preliminary rev 0.6 programmable counter array (pca0) register 20.13. pca0cpm2: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16 ecom capp capn mat tog pwm eccf ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xdc table 20.15. pca0cpm2 register bit descriptions bit name function 7 pwm16 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecom comparator function enable. this bit enables the comparator function. 5 capp capture positive function enable. this bit enables the positive edge capture capability. 4 capn capture negative function enable. this bit enables the negative edge capture capability. 3 mat match function enable. this bit enables the match function. when en ab led, matche s of the pca counter with a module's capture/compare regist er cause the ccf2 bit in the pca0md register to be set to logic 1. 2 tog toggle function enable. this bit enables the toggle function. when en able d, matches of the pca counter with the capture/compare register cause the logic leve l on the cex2 pin to toggle. if the pwm bit is also set to logic 1, the module operates in frequency output mode. 1 pwm pulse width modulation mode enable. this bit enables the pwm function. when enabled, a pulse width modulated signal is out - put on the cex2 pin. 8 to 11-bit pwm is used if pwm16 is cleared; 16-bit mode is used if pwm16 is set to logic 1. if the tog bit is also set, the module operates in frequency output mode. 0 eccf capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccf2) interrupt. 0: disable ccf2 interrupts. 1: enable a capture/compare flag interrupt request when ccf2 is set.
c8051f85x/86x preliminary rev 0.6 173 programmable co unter array (pca0) register 20.14. pca0cpl1: pca capture module low byte bit 7 6 5 4 3 2 1 0 name pca0cpl1 typ e rw r e s e t00000000 sfr address: 0xe9 table 20.16. pca0cpl1 register bit descriptions bit name function 7:0 pca0cpl1 pca capture module low byte. the pca0cpl1 register holds the low byte (lsb) of the 16-bit capture module.this reg - ister address also allows access to the low byte of the corresponding pca channels a u to-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will clear the modules ecom bit to a 0.
c8051f85x/86x 174 preliminary rev 0.6 programmable counter array (pca0) register 20.15. pca0cph1: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cph1 typ e rw r e s e t00000000 sfr address: 0xea table 20.17. pca0cph1 register bit descriptions bit name function 7:0 pca0cph1 pca capture module high byte. the pca0cph1 register holds the high byte (m sb) of the 16-bit capture module.this register address also allows access to the high byte of the corresponding pca channels auto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will set the modules ecom bit to a 1.
c8051f85x/86x preliminary rev 0.6 175 programmable co unter array (pca0) register 20.16. pca0cpl2: pca capture module low byte bit 7 6 5 4 3 2 1 0 name pca0cpl2 typ e rw r e s e t00000000 sfr address: 0xeb table 20.18. pca0cpl2 register bit descriptions bit name function 7:0 pca0cpl2 pca capture module low byte. the pca0cpl2 register holds the low byte (lsb) of the 16-bit capture module.this reg - ister address also allows access to the low byte of the corresponding pca channels a u to-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will clear the modules ecom bit to a 0.
c8051f85x/86x 176 preliminary rev 0.6 programmable counter array (pca0) register 20.17. pca0cph2: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cph2 typ e rw r e s e t00000000 sfr address: 0xec table 20.19. pca0cph2 register bit descriptions bit name function 7:0 pca0cph2 pca capture module high byte. the pca0cph2 register holds the high byte (m sb) of the 16-bit capture module.this register address also allows access to the high byte of the corresponding pca channels auto-reload value for 9 to 11-bit pwm mode. the arsel bit in register pca0pwm con - trols which register is accessed. note: a write to this register will set the modules ecom bit to a 1.
c8051f85x/86x 178 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21. port i/o (port 0, port 1, port 2, crossbar, and port match) digital and analog resources on the c8051f85x/86x family are externally available on the devices multi-purpose i/ o pins. port pins p0.0-p1.7 can be defined as general-pur pose i/o (gpio), assigned to one of the internal digital resources through the crossbar, or assigned to an analog function. port pins p2.0 and p2.1 can be used as gpio. port pin p2.0 is shared with the c2 interface data sign al (c2d). the designer has complete control over which functions are assigned, limited only by the number of physical i/o pins. this resource assignme nt flexibility is achieved through the use of a priority crossbar decoder. no te that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder (figure 21.2 and figure 21.3). the registers xbr0, xbr1 and xbr2 are used to select internal digital functions. the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1). additionally, each bank of port pins (p0, p1, and p2) have two selectable drive strength settings. figure 21.1. port i/o functional block diagram p2.1 p2.0 / c2d port 2 control & config uart0 spi0 smbus0 cmp0 out sysclk pca (cexn) timer 0 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.7 p1.0 port 1 control & config cmp1 out timer 1 timer 2 2 4 2 2 2 1 3 pca (eci) 1 1 1 1 priority crossbar decoder adc0 in cmp0/1 in int0 / int1 port match p0.0 / vref p0.1 / agnd p0.2 p0.3 / extclk p0.4 p0.6 / cnvstr p0.7 p0.5 port 0 control & config
c8051f85x/86x preliminary rev 0.6 179 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21.1. general port i/o initialization port i/o initialization consists of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) for all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port sk ip registers (pnskip). 4. assign port pins to desired peripherals. 5. enable the crossbar (xbare = 1). all port pins must be configured as either analog or digital inputs. any pi ns to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this pr ocess saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; howev er this practice is not recommended. additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in th e pnmdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all pins default to digital inputs on reset. the output driver characteristics of the i/o pins are defined using the port output mode registers (pnmdout). each port output driver can be configured as either open drain or push-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regard less of the pnmdout settings. when the weakpud bit in xbr1 is 0, a weak pullup is enabled for all port i/o configured as open-drain. weakpud does not affect the push-pull port i/o. furthermore, the weak pullup is turned of f on an output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the appropriate values to select the digital i/o functions required by the design. setting the xbare bit in xbr2 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mo de), regardless of the xbrn register settings. for given xbrn register settings, one can determine the i/o pin-ou t using the priority decode table; as an alternative, silicon labs provides configuration utility software to determ ine the port i/o pin-as signments based on the crossbar register settings. the crossbar must be enabled to use port pins as stan dard port i/o in output mode. port output drivers of all crossbar pins are disabled whenever the crossbar is disabled.
c8051f85x/86x 180 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21.2. assigning port i/o pins to analog and digital functions port i/o pins can be assigned to various analog, digital, a nd external interrupt functions. the port pins assigned to analog functions should be configured for analog i/o, an d port pins assigned to digital or external interrupt functions should be configured for digital i/o. 21.2.1. assigning port i/o pins to analog functions table 21.1 shows all available analog functions that requi re po rt i/o assignments. ta ble 21.1 shows the potential mapping of port i/o to each analog function. 21.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assign ed to digital functions or used as gpio. most digital functions rely on the crossbar for pin assignment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. table 21.2 sh ows all digital functions available through the crossbar and the potential mapping of port i/o to each function. table 21.1. port i/o assignment for analog functions analog function potentially assignable port pins sfr(s) used for assignmen t adc input p0.0 - p1.7 amx0p, amx0n, pnskip , pnmdin comparator0 input p0.0 - p1.7 cpt0mx, pnskip, pnmdin comparator1 input p0.0 - p1.7 cpt1mx, pnskip, pnmdin voltage reference (vref) p0.0 ref0cn, pnskip, pnmdin reference ground (agnd) p0.1 ref0cn, pnskip, pnmdin table 21.2. port i/o assignment for digital functions digital function potentially assign able port pins sfr(s) used for assignmen t uart0, spi0, smbus0, cp0, cp0a, cp1, cp1a, sysclk, pca0 (cex0- 2 an d eci) , t0 , t1 or t2. any port pin available for assignment by the cros sbar. this includes p0.0 - p1.7 pins which have their pnskip bit set to 0. note: the cros sbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1, xbr2 any pin used for gpio p0.0 - p2.1 p0skip, p1skip, p2sk ip
c8051f85x/86x preliminary rev 0.6 181 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21.2.3. assigning port i/o pins to fixed digital functions fixed digital functions include external clock input as well a s external event tr igger functions, which can be used to trigger events such as an adc conversion, fire an interrupt or wake the device from idle mode when a transition occurs on a digital i/o pin. the fixed digital functions do not require dedicated pins and will function on both gpio pins and pins in use by the crossbar. fixed digital func tions cannot be used on pins configured for analog i/o. table 21.3 shows all available fixed digital functions a nd the potential mapping of port i/o to each function. table 21.3. port i/o assignment for fixed digital functions function potentially assign able port pins sfr(s) used for assignmen t external interrupt 0 p0.0 - p0.7 it01cf external interrupt 1 p0.0 - p0.7 it01cf conversion start (cnvstr) p0.6 adc0cn external clock input (extclk) p0.3 oscxcn port match p0.0 - p1.7 p0mask, p0mat p1mask, p1mat
c8051f85x/86x 182 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21.3. priority crossbar decoder the priority crossbar decoder assigns a priority to each i/ o function, starting at the top with uart0. when a digital resource is selected, the least-significant unassigned po rt pin is assigned to that resource (excluding uart0, which is always at pins p0.4 and p0.5). if a port pin is assigned, the crossbar skips that pin when assigning the next selected resource. additionally, th e crossbar will skip port pins whose a ssociated bits in the pnskip registers are set. the pnskip registers allow softwa re to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: if a port pin is claimed by a pe ripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.0 if vref is used, p0.1 if agnd is used, p0.3 if the extclk input is enabled, p0.6 if the adc is configured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. the crossbar skip s selected pins as if they were already assigned, and moves to the next unassigned pin. figure 21.2 shows all of the potential peripheral-to-pin as signments available to the crossbar. note that this does not mean any peripheral can always be assigned to the highlighted pins. the ac tual pin assignments are determined by the priority of the enabled peripherals. figure 21.2. crossbar priority decoder - possible pin assignments uart0-tx uart0-rx sysclk pca0-cex0 pca0-cex1 pca0-cex2 pca0-eci timer0-t0 timer1-t1 0 1 2 3 4 5 6 7 p0 port pin number 0 0 0 0 0 0 0 0 p0skip pin skip settings spi0-sck spi0-miso spi0-mosi spi0-nss* 0 1 2 3 4 5 6 7 p1 0 0 0 0 0 0 0 0 p1skip 0 1 p2 the crossbar peripherals are assigned in priority order from top to bottom. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be skipped by setting the corresponding bit in pnskip to 1. * nss is only pinned out when the spi is in 4-wire mode. smb0-sda smb0-scl qsop-24 package vref extclk cnvstr c2d qfn-20 package pins not available on crossbar timer2-t2 cmp0-cp0 cmp0-cp0a cmp1-cp1 cmp1-cp1a n/a soic-16 package n/a n/a n/a n/a
c8051f85x/86x preliminary rev 0.6 183 port i/o (port 0, port 1, po rt 2, crossbar, and port match) registers xbr0, xbr1 and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assigns both pins associated with the smbus (sda and scl); when uart0 is selected, the crossb ar assigns both pins associated with uart0 (tx and rx). uart0 pin assignments are fixed for bootloading purposes: uart0 tx is always assigned to p0.4; uart0 rx is always assigned to p0.5. standard port i/os appear contiguous ly after the prioritized functions have been assigned. figure 21.3 shows an example of the resulting pin a ssignments of the device with uart0 and spi0 enabled and the extclk (p0.3) pin skipped (p0skip = 0x08). uart0 is the highest priority and it will be assigned first. the uart0 pins can only appear on p0.4 and p0.5, so that is where it is assigned. the next-highest enabled peripheral is spi0. p0.0, p0.1 and p0.2 are free, so spi0 takes these three pins. th e fourth pin, nss, is routed to p0.6 because p0.3 is skipped and p0.4 and p0.5 are already oc cupied by the uart. the other pins on the device are available for use as general-purpose digital i/o or analog functions. figure 21.3. crossbar priority decoder example note: the spi can be operated in either 3-wire or 4-wire m odes, pending the state of the nssmd1Cnssmd0 bits in register spi0cn. according to the spi mode, the nss si gnal may or may not be routed to a port pin. the order in which smbus pins are assigned is defined by the swap bit in the smb0tc register. uart0-tx uart0-rx sysclk pca0-cex0 pca0-cex1 pca0-cex2 pca0-eci timer0-t0 timer1-t1 0 1 2 3 4 5 6 7 p0 port pin number 0 0 0 1 0 0 0 0 p0skip pin skip settings spi0-sck spi0-miso spi0-mosi spi0-nss* 0 1 2 3 4 5 6 7 p1 0 0 0 0 0 0 0 0 p1skip 0 1 p2 the crossbar peripherals are assigned in priority order from top to bottom. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be skipped by setting the corresponding bit in pnskip to 1. * nss is only pinned out when the spi is in 4-wire mode. smb0-sda smb0-scl qsop-24 package vref extclk cnvstr c2d qfn-20 package pins not available on crossbar timer2-t2 cmp0-cp0 cmp0-cp0a cmp1-cp1 cmp1-cp1a n/a soic-16 package n/a n/a n/a n/a
c8051f85x/86x 184 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21.4. port i/o m odes of operation port pins are configured by firmware as digital or analog i/o using the pnmdin registers. on reset, all port i/o cells default to a high impedance state with weak pull-ups enabled. until the crossbar is enabled, both the high and low port i/o drive circuits are explicitly di sabled on all crossbar pins. port pins co nfigured as digital i/o may still be used by analog peripherals; however, this practice is no t recommended and may result in measurement errors. 21.4.1. configurin g port pins for analog modes any pins to be used for analog functions should be c onfigur ed for analog mode. when a pin is configured for analog i/o, its weak pullup, digital driver, and digital receiv er are disabled. port pins co nfigured for analog functions will always read back a value of 0 in the corresponding pn port latch register. to co nfigure a pin as analog, the following steps should be taken: 1. clear the bit associated with the pin in the pnmdin register to 0. this selects analog mode for the pin. 2. set the bit associat ed with the pin in the pn register to 1. 3. skip the bit associated with the pin in the pnskip register to ensure the crossbar does not attempt to assign a function to the pin. 21.4.2. configurin g po rt pins for digital modes any pins to be used by digital peripherals or as gpio should b e configured as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output modes (push-pull or ope n-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the supply rails based on the output logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to the low- side rail when the output logic value is 0 and become high impedance inputs (both high low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the high- side rail to ensure the digital input is at a defined logic st ate. weak pull-ups are disabled when the i/o cell is driven low to minimize power consumption, and they may be globally disabled by setti ng weakpud to 1. the user should ensure that digital i/o are alwa ys internally or externally pulled or driven to a valid logic state to minimize power consumption. port pins configured for digital i/o al ways read back the logic state of the port pad, regardless of the output logic value of the port pin. to configure a pin as digital input: 1. set the bit associated with the pin in the pnmdin register to 1. this selects digital mode for the pin. 2. clear the bit associated with the pin in the pnmdout r egister to 0. this configures the pin as open-drain. 3. set the bit associated with the pin in the pn register to 1. this tells the output driver to drive logic high. because the pin is configured as open-drain, the high-s ide driver is not active, and the pin may be used as an input. open-drain outputs are configured exac tly as digital inputs. however, the pin may be driven low by an assigned peripheral, or by writing 0 to the associated bit in the pn register if the signal is a gpio. to configure a pin as a digital, push-pull output: 1. set the bit associated with the pin in the pnmdin register to 1. this selects digital mode for the pin. 2. set the bit associated with the pin in the pnmdout register to 1. this configures the pin as push-pull. if a digital pin is to be used as a general-purpose i/o, or with a digital function that is not part of the crossbar, the bit associated with the pin in the pnskip register can be set to 1 to ensure the crossbar does not attempt to assign a function to the pin. 21.4.3. port drive strength port drive strength can be controlled on a port-by-port basis using the prtdrv regist er. each port has a bit in prtdrv to select the high or low drive strength setting for all pins on that port. by default, all ports are configured for high drive strength.
c8051f85x/86x preliminary rev 0.6 185 port i/o (port 0, port 1, po rt 2, crossbar, and port match) figure 21.4. port i/o cell block diagram 21.5. port match port match functionality allows system events to be triggered by a logic value change on one or more port i/o pins. a software controlled value stored in the pnmatch register s specifies the expected or normal logic values of the associated port pins (for example, p0match.0 would corr espond to p0.0). a port mismatch event occurs if the logic levels of the ports input pins no longer match the softwa re controlled value. this allo ws software to be notified if a certain change or pattern occurs on the input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which pins should be compared against the pnmatch registers. a port mismatch event is generated if (pn & pnmask) does no t equal (pnmatch & pnmask) for all ports with a pnmat and pnmask register. a port mismatch event may be used to generate an interrup t or wake the device from idle mode. see the interrupts and power options chapters for more details on interrupt and wake-up sources. 21.6. direct read/write access to port i/o pins all port i/o are accessed through corresponding special fu nction registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value wri tten to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of th e port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the exception to this is the execution of the read-modify-write instructions that target a port latch register as the destinat ion. the read-modify-write instructio ns when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, w hen the destination is an individual bit in a port sfr. for these instructions, the value of the latch regist er (not the pin) is read, modified, and written back to the sfr. gnd vdd vdd (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x C output logic value (port latch or crossbar) xbare (crossbar enable) px.x C input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable)
c8051f85x/86x 186 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) 21.7. port i/o and pin configur ation control registers register 21.1. xbr0: port i/o crossbar 0 bit 7 6 5 4 3 2 1 0 name syscke cp1ae cp1e cp0ae cp0e smb0e spi0e urt0e ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0xe1 table 21.4. xbr0 register bit descriptions bit name function 7 syscke sysclk output enable. 0: sysclk unavailable at port pin. 1: sysclk output routed to port pin. 6 cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. 5 cp1e comparator1 output enable. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. 4 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 3 cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 2 smb0e smbus0 i/o enable. 0: smbus0 i/o unavailable at port pins. 1: smbus0 i/o routed to port pins. 1 spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. the spi can be assigned either 3 or 4 gpio pins. 0 urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx, rx routed to port pins p0.4 and p0.5.
c8051f85x/86x preliminary rev 0.6 187 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.2. xbr1: port i/o crossbar 1 bit 7 6 5 4 3 2 1 0 name reserved t2e t1e t0e ecie pca0me ty per rwrwrwrwrw rw r e s e t00000000 sfr address: 0xe2 table 21.5. xbr1 register bit descriptions bit name function 7:6 reserved must write reset value. 5 t2e t2 enable. 0: t2 unavailable at port pin. 1: t2 routed to port pin. 4 t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 3 t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 2 ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 1:0 pca0me pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins.
c8051f85x/86x 188 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.3. xbr2: port i/o crossbar 2 bit 7 6 5 4 3 2 1 0 name weakpud xbare reserved ty pe rw rw r r e s e t00000000 sfr address: 0xe3 table 21.6. xbr2 register bit descriptions bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5:0 reserved must write reset value.
c8051f85x/86x preliminary rev 0.6 189 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.4. prtdrv: port drive strength bit 7 6 5 4 3 2 1 0 name reserved p2drv p1drv p0drv ty pe r rwrwrw r e s e t00000111 sfr address: 0xf6 table 21.7. prtdrv register bit descriptions bit name function 7:3 reserved must write reset value. 2 p2drv port 2 drive strength. 0: all pins on p2 use low drive strength. 1: all pins on p2 use high drive strength. 1 p1drv port 1 drive strength. 0: all pins on p1 use low drive strength. 1: all pins on p1 use high drive strength. 0 p0drv port 0 drive strength. 0: all pins on p0 use low drive strength. 1: all pins on p0 use high drive strength.
c8051f85x/86x 190 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.5. p0mask: port 0 mask bit 7 6 5 4 3 2 1 0 name p0mask typ e rw r e s e t00000000 sfr address: 0xfe table 21.8. p0mask register bit descriptions bit name function 7:0 p0mask port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.x pin logic valu e i s ignored and will cause a port mismatch event. 1: p0.x pin logic value is compared to p0mat.x.
c8051f85x/86x preliminary rev 0.6 191 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.6. p0mat: port 0 match bit 7 6 5 4 3 2 1 0 name p0mat typ e rw r e s e t11111111 sfr address: 0xfd table 21.9. p0mat register bit descriptions bit name function 7:0 p0mat port 0 match value. match comparison value used on p0 pins for bits in p0mask which are set to 1. 0: p0.x pin logic value is compared with logic low. 1: p0.x pin logic value is comp ared with logic high.
c8051f85x/86x 192 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.7. p0: port 0 pin latch bit 7 6 5 4 3 2 1 0 name p0 typ e rw r e s e t11111111 sfr address: 0x80 (bit-addressable) table 21.10. p0 register bit descriptions bit name function 7:0 p0 port 0 data. writing this register sets the port latch logi c va lue for the associated i/o pins configured as digital i/o. reading this register returns the logic value at the pin , regardless if it is configured as output or input.
c8051f85x/86x preliminary rev 0.6 193 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.8. p0mdin: port 0 input mode bit 7 6 5 4 3 2 1 0 name p0mdin typ e rw r e s e t11111111 sfr address: 0xf1 table 21.11. p0mdin register bit descriptions bit name function 7:0 p0mdin port 0 input mode. port pins configured for analog mode have t heir weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.x pin is configured for analog mode. 1: corresponding p0.x pin is configured for digital mode.
c8051f85x/86x 194 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.9. p0mdout: port 0 output mode bit 7 6 5 4 3 2 1 0 name p0mdout typ e rw r e s e t00000000 sfr address: 0xa4 table 21.12. p0mdout register bit descriptions bit name function 7:0 p0mdout port 0 output mode. these bits are only applicable when the pin is configured for digital mode using the p0 md in register. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull.
c8051f85x/86x preliminary rev 0.6 195 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.10. p0skip: port 0 skip bit 7 6 5 4 3 2 1 0 name p0skip typ e rw r e s e t00000000 sfr address: 0xd4 table 21.13. p0skip register bit descriptions bit name function 7:0 p0skip port 0 skip. these bits select port pins to be skipped by the cr ossbar decoder. port pins used for ana - log, special functions or gpio should be skipped. 0: corresponding p0.x pin is not skipped by the crossbar. 1: corresponding p0.x pin is skipped by the crossbar.
c8051f85x/86x 196 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.11. p1mask: port 1 mask bit 7 6 5 4 3 2 1 0 name p1mask typ e rw r e s e t00000000 sfr address: 0xee table 21.14. p1mask register bit descriptions bit name function 7:0 p1mask port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.x pin logic valu e i s ignored and will cause a port mismatch event. 1: p1.x pin logic value is compared to p1mat.x. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
c8051f85x/86x preliminary rev 0.6 197 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.12. p1mat: port 1 match bit 7 6 5 4 3 2 1 0 name p1mat typ e rw r e s e t11111111 sfr address: 0xed table 21.15. p1mat register bit descriptions bit name function 7:0 p1mat port 1 match value. match comparison value used on p1 pins for bits in p1mask which are set to 1. 0: p1.x pin logic value is compared with logic low. 1: p1.x pin logic value is comp ared with logic high. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
c8051f85x/86x 198 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.13. p1: port 1 pin latch bit 7 6 5 4 3 2 1 0 name p1 typ e rw r e s e t11111111 sfr address: 0x90 (bit-addressable) table 21.16. p1 register bit descriptions bit name function 7:0 p1 port 1 data. writing this register sets the port latch logi c va lue for the associated i/o pins configured as digital i/o. reading this register returns the logic value at the pin , regardless if it is configured as output or input. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
c8051f85x/86x preliminary rev 0.6 199 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.14. p1mdin: port 1 input mode bit 7 6 5 4 3 2 1 0 name p1mdin typ e rw r e s e t11111111 sfr address: 0xf2 table 21.17. p1mdin register bit descriptions bit name function 7:0 p1mdin port 1 input mode. port pins configured for analog mode have t heir weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.x pin is configured for analog mode. 1: corresponding p1.x pin is configured for digital mode. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
c8051f85x/86x 200 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.15. p1mdout: port 1 output mode bit 7 6 5 4 3 2 1 0 name p1mdout typ e rw r e s e t00000000 sfr address: 0xa5 table 21.18. p1mdout register bit descriptions bit name function 7:0 p1mdout port 1 output mode. these bits are only applicable when the pin is configured for digital mode using the p1 md in register. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
c8051f85x/86x preliminary rev 0.6 201 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.16. p1skip: port 1 skip bit 7 6 5 4 3 2 1 0 name p1skip typ e rw r e s e t00000000 sfr address: 0xd5 table 21.19. p1skip register bit descriptions bit name function 7:0 p1skip port 1 skip. these bits select port pins to be skipped by the cr ossbar decoder. port pins used for ana - log, special functions or gpio should be skipped. 0: corresponding p1.x pin is not skipped by the crossbar. 1: corresponding p1.x pin is skipped by the crossbar. note: port 1 consists of 8 bits (p1.0-p1.7) on qsop24 packages and 7 bits (p1.0-p1.6) on qfn20 packages and 4 bits (p1.0-p1.3) on soic16 packages.
c8051f85x/86x 202 preliminary rev 0.6 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.17. p2: port 2 pin latch bit 7 6 5 4 3 2 1 0 name reserved p2 typ e r rw r e s e t00000011 sfr address: 0xa0 (bit-addressable) table 21.20. p2 register bit descriptions bit name function 7:2 reserved must write reset value. 1:0 p2 port 2 data. writing this register sets the port latch logi c va lue for the associated i/o pins configured as digital i/o. reading this register returns the logic value at the pin , regardless if it is configured as output or input. note: port 2 consists of 2 bits (p2.0-p2.1) on qsop24 devices and 1 bit (p2.0) on qfn20 and soic16 packages.
c8051f85x/86x preliminary rev 0.6 203 port i/o (port 0, port 1, po rt 2, crossbar, and port match) register 21.18. p2mdout: port 2 output mode bit 7 6 5 4 3 2 1 0 name reserved p2mdout typ e r rw r e s e t00000000 sfr address: 0xa6 table 21.21. p2mdout register bit descriptions bit name function 7:2 reserved must write reset value. 1:0 p2mdout port 2 output mode. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. note: port 2 consists of 2 bits (p2.0-p2.1) on qsop24 devices and 1 bit (p2.0) on qfn20 and soic16 packages.
c8051f85x/86x 204 preliminary rev 0.6 reset sources an d supply monitor 22. reset sources and supply monitor reset circuitry allows the controller to be easily placed in a predefined default condition. upon entering this reset state, the following events occur: ?? cip-51 halts program execution ?? special function registers (sfrs) are initialized to their defined reset values ?? external port pins are placed in a known state ?? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any previously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effect ively lost, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain, low-drive mode. weak pullups are enabled during and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. note that during a power-on event, there may be a short delay before the por circuitry fires and the rst pin is driven low. during that time, the rst pin will be weakly pulled to the v dd supply pin. on exit from the reset state, the pr ogram counter (pc) is reset, the watc hdog timer is enabled and the system clock defaults to the internal oscillator. program exec ution begins at location 0x0000. figure 22.1. reset sources reset sources rst supply monitor or power-up missing clock detector watchdog timer software reset comparator 0 system reset flash error
c8051f85x/86x preliminary rev 0.6 205 reset sources and supply monitor 22.1. power-on reset during power-up, the por circuit will fi re. when por fires, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . two delays are present during the su pply ramp time. first, a delay will occur before the por circuitry fires and pulls the rst pin low. a second delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 22.2. plots the power-on reset timing. for ramp times less than 1 ms, the power-on reset time (t por ) is typically less than 0.3 ms. additi onally, the power supply must reach v rst before the por circuit will release the device from reset. on exit from a power-on reset, the pors f flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc register are indeterm inate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was the cause of reset. the content of internal data memory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 22.2. power-on reset timing power-on reset rst t volts logic high logic low t por v d d
c8051f85x/86x 206 preliminary rev 0.6 reset sources an d supply monitor 22.2. power-fail reset / supply monitor c8051f85x/86x devices have a supply monitor that is enab led and selected as a reset source after each power-on. the supply monitor senses the voltage on the device vdd supply and can generate a reset if the supply drops below the corresponding threshold. this monitor is enabled and enabled as a reset source after initial power-on to protect the device until vdd is an adequate and stable voltage. when enabled and selected as a reset source, any power down transition or power irregularity that causes vdd to drop below the reset th reshold will drive the rst pin low and hold the core in a reset state. when vdd returns to a level above the reset threshold, the monitor will release the co re from the reset state. th e reset status can then be read using the device reset sources module. after a power- fail reset, the porf flag reads 1 and all of the other reset flags in the rstsrc register are indeterminate. the power-on reset delay (t por ) is not incurred after a supply monitor reset. the contents of ram should be presumed invalid after a vdd monitor reset. the enable state of the vdd supply monitor and its selectio n as a reset source is not altered by device resets. for example, if the vdd supply monitor is de-selected as a reset source and disabled by software, and then firmware performs a software reset, the v dd supply monitor will remain disabled and de-selected after the reset. to protect the integrity of flash contents, the vdd supply monitor must be enabled and selected as a reset source if software contains routines that er ase or write flash memory. if the vdd supply monitor is not enabled, any erase or write performed on fl ash memory will be ignored. figure 22.3. vdd supply monitor threshold 22.3. enabling the vdd monitor the vdd supply monitor is enabled by default. however, in systems which disable the supply monitor, it must be enabled before selecting it as a reset source. selecting the vdd supply monitor as a reset source before it has stabilized may generate a system reset. in systems where this reset would be undesirable, a delay should be introduced between enabling the vdd supply monitor and se lecting it as a reset source. no delay should be introduced in systems where software contains routines that erase or write flash memory. the procedure for enabling the vdd supply monitor and selecting it as a reset source is: 1. enable the vdd supply monitor (vmonen = 1). 2. wait for the vdd supply monitor to stabilize (optional). 3. enable the vdd monitor as a reset source in the rstsrc register. t volts vdd reset threshold (v rst ) vdd monitor reset rst
c8051f85x/86x preliminary rev 0.6 207 reset sources and supply monitor 22.4. external reset the external rst pin provides a means for external circuitry to fo rce the device into a reset state. asserting an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. the pinrsf flag is set on ex it from an external reset. 22.5. missing cl ock detector reset the missing clock detector (mcd) is a one-s hot circuit that is triggered by th e system clock. if the system clock remains high or low for more than the mcd time window, the one-shot will ti me out and generate a reset. after a mcd reset, the mcdrsf flag will read 1, signifying the mcd as the reset so urce; otherwise, th is bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock de tector; writing a 0 disables it. the state of the rst pin is unaffected by this reset. 22.6. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag. comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted reset. the comparator0 reset is acti ve-low: if the non-inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, the c0rsef flag will read 1 signifying comparat or0 as the reset source; otherwise, th is bit reads 0. the state of the rst pin is unaffected by this reset. 22.7. watchdog timer reset the programmable watchdog timer (wdt) can be used to prevent software from running out of control during a system malfunction. the wdt function can be enabled or disabled by software as described in the watchdog timer section. if a system malfunction prevents user software from updating the wdt, a reset is generated and the wdtrsf bit is set to 1. the state of the rst pin is unaffected by this reset. 22.8. flash error reset if a flash read/write/era se or program read targets an illegal address, a system rese t is generated. this may occur due to any of the following: ?? a flash write or erase is attempted above user code space. ?? a flash read is attempted above user code space. ?? a program read is attempted above user code space (i.e. a branch instruction to the reserved area). ?? a flash read, write or erase attempt is re stricted due to a flash security setting. the ferror bit is set following a flash error reset. the state of the rst pin is unaffected by this reset. 22.9. software reset software may force a reset by writing a 1 to the swrsf bit. the swrsf bit will read 1 following a software forced reset. the state of the rst pin is unaffected by this reset.
c8051f85x/86x 208 preliminary rev 0.6 reset sources an d supply monitor 22.10. reset sources control registers register 22.1. spi0cfg: spi0 configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpo l s lvsel nssin srmt rxbmt t y p err wr wr wrrrr r e s e t00000111 sfr address: 0xa1 table 22.1. spi0cfg register bit descriptions bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in p rogress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. 1: data centered on second edge of sck period. 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is hi gh (slave not selected). this bit does not indi - cate the instantaneous value at the nss pin, but rather a de-glitched version of the pin in put. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is pr esent on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been transferred in/out of the shif t register , and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the receive buf f er has been read and contains no new information. if there is new information available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum sett ling time for the slave device.
c8051f85x/86x preliminary rev 0.6 209 reset sources and supply monitor register 22.2. spi0cn: spi0 control bit 7 6 5 4 3 2 1 0 name spif wcol modf rxovrn nssmd txbmt spien ty pe rw rw rw rw rw r rw r e s e t00000110 sfr address: 0xf8 (bit-addressable) table 22.2. spi0cn register bit descriptions bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at th e en d of a data transfer. if spi interrupts are enabled, an interrupt will be generated. this bit is not automatically cl eared by hardware, and must be cleared by software. 6 wcol write collision flag. this bit is set to logic 1 if a write to spi0d a t is attempted when txbmt is 0. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be written. if spi interrupts ar e enabled, an inte rrupt will be generat ed. this bit is not automatically cleared by hardware, and must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware when a mast er mode collision is detected (nss is low, msten = 1, and nssmd = 01). if spi interrupts are enabled , an interrupt will be generated. this bit is not automatically cl eared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware when the receive buf fer still ho lds unread data from a previous transfer and the last bit of the curr ent transfer is shifted into the spi0 shift reg - ister. if spi interrupts are enabled, an interrupt will be generated. this bit is not automat - ically cleared by hardware, and must be cleared by software. 3:2 nssmd slave select mode. selects between the following nss operation modes: 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efau lt). nss is an input to the device. 10: 4-wire single-master mode. nss is an output and logic low. 11: 4-wire single-master mode. ns s is a n output and logic high. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new data has been written to the transmit buf fer . when data in the transmit buffer is transferred to the spi shift regist er, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled.
c8051f85x/86x 210 preliminary rev 0.6 reset sources an d supply monitor register 22.3. spi0ckr: spi0 clock rate bit 7 6 5 4 3 2 1 0 name spi0ckr typ e rw r e s e t00000000 sfr address: 0xa2 table 22.3. spi0ckr register bit descriptions bit name function 7:0 spi0ckr spi0 clock rate. these bits determine the frequency of the sck o utput when the spi0 module is config - ured for master mode operation. the sck clock frequency is a divided version of the sys tem clock , and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 f sck sysclk 2 spi0ckr 1 + ?? ? ----------------------------------------------- =
c8051f85x/86x preliminary rev 0.6 211 reset sources and supply monitor register 22.4. spi0dat: spi0 data bit 7 6 5 4 3 2 1 0 name spi0dat typ e rw r e s e t00000000 sfr address: 0xa3 table 22.4. spi0dat register bit descriptions bit name function 7:0 spi0dat spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0 - dat places the data into the transmit buffer and initiates a transfer when in master mode. a re ad of spi0 dat returns the contents of the receive buffer. register 22.5. rstsrc: reset source bit 7 6 5 4 3 2 1 0 name reserved ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf ty pe r r rw rw r rw rw r r e s e t0xxxxxxx sfr address: 0xef table 22.5. rstsrc register bit descriptions bit name function 7 reserved must write reset value. 6 ferror flash error reset flag. this read-only bit is set to 1 if a flash re ad/w rite/erase error c aused the last reset. 5 c0rsef comparator0 reset enable and flag. read: this bit reads 1 if comparator0 caused the last reset. write: writing a 1 to this bit enables comparator0 (active-low) as a reset source. notes: 1. reads and writes of the rstsrc register access different logic in the device. reading the register always returns status information to indicate the source of the most recent reset. writing to the register activates certain options as reset sources. it is recommended to not use any kind of read-modify-write operation on this register. 2. when the porsf bit reads back 1 all other rstsrc flags are indeterminate. 3. writing 1 to the porsf bit when the supply monitor is not enabled and stabilized may cause a system reset.
c8051f85x/86x 212 preliminary rev 0.6 reset sources an d supply monitor supply monitor control registers 4 swrsf software reset force and flag. read: this bit reads 1 if last rese t was cau sed by a write to swrsf. write: writing a 1 to this bit forces a system reset. 3 wdtrsf watchdog timer reset flag. this read-only bit is set to 1 if a watchd og timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. read: this bit reads 1 if a missing clock detector timeout caused the last reset. write: writing a 1 to this bit enables the mi ssing clock detector. the mcd triggers a reset if a missing clock condition is detected. 1 porsf power-on / supply monitor reset flag, and supply monitor reset enable. read: this bit reads 1 anytime a power-on or supply monitor reset has occurred. write: writing a 1 to this bit enables the supp ly monitor as a reset source. 0 pinrsf hw pin reset flag. this read-only bit is set to 1 if the rst pin caused the last reset. register 22.6. vdm0cn: supply monitor control bit 7 6 5 4 3 2 1 0 name vdmen vddstat reserved typ e rw r r r e s e txxxxxxxx sfr address: 0xff table 22.6. vdm0cn register bit descriptions bit name function 7 vdmen supply monitor enable. this bit turns the supply monitor circuit on/off. the supply monitor cannot generate sys - tem resets until it is also selected as a rese t source in register rstsrc. selec ting the supply monitor as a re set source before it has stabilized may generat e a system reset. in systems where this reset would be undesirable, a delay should be introduced between enabling the supply monitor and selecting it as a reset source. 0: supply monitor disabled. 1: supply monitor enabled. table 22.5. rstsrc register bit descriptions bit name function notes: 1. reads and writes of the rstsrc register access different logic in the device. reading the register always returns status information to indicate the source of the most recent reset. writing to the register activates certain options as reset sources. it is recommended to not use any kind of read-modify-write operation on this register. 2. when the porsf bit reads back 1 all other rstsrc flags are indeterminate. 3. writing 1 to the porsf bit when the supply monitor is not enabled and stabilized may cause a system reset.
c8051f85x/86x preliminary rev 0.6 213 reset sources and supply monitor 6 vddstat supply status. this bit indicates the current power s upply st atus (supply monitor output). 0: v dd is at or below the supply monitor threshold. 1: v dd is above the supply monitor threshold. 5:0 reserved must write reset value. table 22.6. vdm0cn register bit descriptions bit name function
c8051f85x/86x 214 preliminary rev 0.6 serial peripheral interface (spi0) 23. serial peripheral interface (spi0) the serial peripheral interface (spi0) provides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single spi bus. the slave-select (nss) signal can be config ured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environmen t, avoiding contention on th e spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional genera l purpose port i/o pins can be used to select multiple slave devices in master mode. figure 23.1. spi0 block diagram spi0 shift register miso mosi clock rate generator sysclk bus control master or slave sck polarity sck phase nss control sck nss spi0dat tx buffer rx buffer
c8051f85x/86x preliminary rev 0.6 215 serial peripheral interface (spi0) 23.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 23.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output from a master device and an input to slave devices. it is used to seria lly transfer data from the master to the slave. this signal is an output when spi0 is operating as a master and an input when spi0 is operating as a slave. data is transferred most-si gnificant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 23.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a sla ve device and an input to the master device. it is used to serially transfer data from the slave to the mast er. this signal is an input when spi0 is operating as a master and an output when spi0 is oper ating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance state when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not selected. when acting as a slave in 3-wi re mode, miso is always driven by the msb of the shift register. 23.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device a nd an input to sl ave devices. it is used to synchronize the transfer of data betw een the master and slave on the mosi and miso lines. spi0 generates this signal when operating as a master. the sck signal is ig nored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 23.1.4. slave select (nss) the function of the slave-select (nss) sig nal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possible mo des that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire sl ave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3- wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mo de: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss select s the spi0 device. when operating as a master, a 1-to- 0 transition of the nss signal disables the master func tion of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire mast er mode: spi0 operates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determines what logic level th e nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 23.2, figure 23.3, and figure 23.4 for typica l connection diagrams of th e various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other mo des, the nss signal will be mapped to a pin on the device.
c8051f85x/86x 216 preliminary rev 0.6 serial peripheral interface (spi0) 23.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bu s. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data regi ster (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmi t buffer is moved to the shift register, and a data transfer begins. the spi0 master immedi ately shifts out the data serially on the mosi line while providing the serial clock on sck. the sp if (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabled, an interrupt request is generated when the spi f flag is set. while the spi0 master transfers data to a slave on the mosi line, the addressed sp i slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit- complete and receive-data-ready flag. the data byte received from the slave is transferred msb-first into the master's shift register. when a byte is fully shifted into the register, it is moved to the re ceive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single- master mode, and 4-wire single-master mode. the defa ult, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another master is accessing th e bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disabl e the spi master device, and a mode fault is generated (modf, spi0cn.5 = 1). mode fault will gen erate an interrupt if enabled. spi0 must be manually re -enabled in software under these circumstances. in multi-master systems, devices will ty pically default to being slave devices while they are not acting as the system master device . in multi-master mode, slave devices can be addressed individually (if needed) using general-purpose i/o pins . figure 23.2 shows a connection diagram between two master devices and a single slave in multiple-master mode. 3-wire single-master mode is active wh en nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an external port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 23.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in this mo de, nss is configured as an output pin, and can be used as a slave-select signal for a singl e spi device. in this mode, the output value of nss is controlled (in software) with the bit nssmd0 (spi0cn.2). additional slav e devices can be addressed using general-purpose i/o pins. figure 23.4 shows a connection diagram for a master device and a slave device in 4- wire mode.
c8051f85x/86x preliminary rev 0.6 217 serial peripheral interface (spi0) figure 23.2. multiple-master mode connection diagram figure 23.3. 3-wire single master and 3-wire single slave mode connection diagram figure 23.4. 4-wire single master mode and 4-wire slave mode connection diagram master device 1 miso mosi sck nss slave device miso mosi sck nss master device 2 miso mosi sck nss port pin port pin slave device master device miso mosi sck miso mosi sck slave device master device miso mosi sck miso mosi sck nss nss
c8051f85x/86x 218 preliminary rev 0.6 serial peripheral interface (spi0) 23.3. spi0 slave mode operation when spi0 is enabled and not configured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin and out through the miso pin by a master device controlling th e sck signal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been sh ifted through the shift register, the spif flag is set to logic 1, and the byte is copied into the receive buffer. da ta is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transfe rred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the content s of the transmit buffer will immediately be transferred into the shift register. when the shift register already contains data, the spi will load the shift register with the trans mit buffers contents after the last sck edge of the ne xt (or current) spi transfer. when configured as a slave, spi0 can be configured for 4- wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0c n.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital i nput. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of nss. note that the nss si gnal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 23.4 shows a connection diagram between two slave devices in 4-wire sl ave mode and a master device. the 3-wire slave mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (s pi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin th rough the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode, spi0 must be th e only slave device present on the bus. it is important to note that in 3-wire slave mode there is no external me ans of resetting the bit counter that determines when a full byte has been received. the bit counter can only be rese t by disabling and re-enablin g spi0 with the spien bit. figure 23.3 shows a connection diagram between a slav e device in 3-wire slave mode and a master device. 23.4. spi0 interrupt sources when spi0 interrupts are enab led, the following four flag s will generate an interr upt when they are set to logic 1: all of the following bits must be cleared by software. ?? the spi interrupt flag, spif ( spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ?? the write collision flag, wcol (spi0cn. 6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift re gister. when this occurs, the write to spi0dat will be ignored, and the transmit buff er will not be written.this flag can occur in all spi0 modes. ?? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 and allow another master device to access the bus. ?? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread by te from a previous transfer. the new byte is not transferred to the receive buffer, allowing t he previously received data byte to be read. the data byte which caused the overrun is lost. 23.5. serial clock phase and polarity four combinations of serial clock phase and polarity ca n be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit (spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be configured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 23.5. for slave mode, the clock and data relationships are shown in figure 23.6 and figure 23.7. note that ckpha should be set to 0 on both the master and sl ave spi when communicating between two silicon labs c8051 devices.
c8051f85x/86x preliminary rev 0.6 219 serial peripheral interface (spi0) the spi0 clock rate register (spi0ckr) co ntrols the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whiche ver is slower. when the spi is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues sck, nss (in 4-wire slave mode), and the serial input data synchronously with the slaves system clock. if the master issues sck, nss, and the serial input data asyn chronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock fr equency. in the special case where the master only wants to transmit data to the slave and does not need to receiv e data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issues sck, nss, and the seri al input data synchronously with the slaves system clock. figure 23.5. master mode data/clock timing figure 23.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0)
c8051f85x/86x 220 preliminary rev 0.6 serial peripheral interface (spi0) figure 23.7. slave mode data/clock timing (ckpha = 1) 23.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. figure 23.8. spi master timing (ckpha = 0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih
c8051f85x/86x preliminary rev 0.6 221 serial peripheral interface (spi0) figure 23.9. spi master timing (ckpha = 1) figure 23.10. spi slave timing (ckpha = 0) sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz
c8051f85x/86x 222 preliminary rev 0.6 serial peripheral interface (spi0) figure 23.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
c8051f85x/86x preliminary rev 0.6 223 serial peripheral interface (spi0) table 23.1. spi slave timing parameters parameter description min max units master mode timing (see figure 23.8 and figure 23.9 ) t mckh sck high time 1 x t sysclk ns t mckl sck low time 1 x t sysclk ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ns t mih sck shift edge to miso change 0 ns slave mode timing (see figu re 23.10 and figure 23.11 ) t se nss falling to first sck edge 2 x t sysclk ns t sd last sck edge to nss rising 2 x t sysclk ns t sez nss falling to miso valid 4 x t sysclk ns t sdz nss rising to miso high-z 4 x t sysclk ns t ckh sck high time 5 x t sysclk ns t ckl sck low time 5 x t sysclk ns t sis mosi valid to sck sample edge 2 x t sysclk ns t sih sck sample edge to mosi change 2 x t sysclk ns t soh sck shift edge to miso change 4 x t sysclk ns t slh last sck edge to miso change ? (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk).
c8051f85x/86x 224 preliminary rev 0.6 serial peripheral interface (spi0) 23.7. spi control registers register 23.1. spi0cfg: spi0 configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpo l s lvsel nssin srmt rxbmt t y p err wr wr wrrrr r e s e t00000111 sfr address: 0xa1 table 23.2. spi0cfg register bit descriptions bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in p rogress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. 1: data centered on second edge of sck period. 4 ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is hi gh (slave not selected). this bit does not indi - cate the instantaneous value at the nss pin, but rather a de-glitched version of the pin in put. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is pr esent on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been transferred in/out of the shif t register , and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the receive buf f er has been read and contains no new information. if there is new information available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum sett ling time for the slave device.
c8051f85x/86x preliminary rev 0.6 225 serial peripheral interface (spi0) register 23.2. spi0cn: spi0 control bit 7 6 5 4 3 2 1 0 name spif wcol modf rxovrn nssmd txbmt spien ty pe rw rw rw rw rw r rw r e s e t00000110 sfr address: 0xf8 (bit-addressable) table 23.3. spi0cn register bit descriptions bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at th e en d of a data transfer. if spi interrupts are enabled, an interrupt will be generated. this bit is not automatically cl eared by hardware, and must be cleared by software. 6 wcol write collision flag. this bit is set to logic 1 if a write to spi0d a t is attempted when txbmt is 0. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be written. if spi interrupts ar e enabled, an inte rrupt will be generat ed. this bit is not automatically cleared by hardware, and must be cleared by software. 5 modf mode fault flag. this bit is set to logic 1 by hardware when a mast er mode collision is detected (nss is low, msten = 1, and nssmd = 01). if spi interrupts are enabled , an interrupt will be generated. this bit is not automatically cl eared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware when the receive buf fer still ho lds unread data from a previous transfer and the last bit of the curr ent transfer is shifted into the spi0 shift reg - ister. if spi interrupts are enabled, an interrupt will be generated. this bit is not automat - ically cleared by hardware, and must be cleared by software. 3:2 nssmd slave select mode. selects between the following nss operation modes: 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efau lt). nss is an input to the device. 10: 4-wire single-master mode. nss is an output and logic low. 11: 4-wire single-master mode. ns s is a n output and logic high. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new data has been written to the transmit buf fer . when data in the transmit buffer is transferred to the spi shift regist er, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled.
c8051f85x/86x 226 preliminary rev 0.6 serial peripheral interface (spi0) register 23.3. spi0ckr: spi0 clock rate bit 7 6 5 4 3 2 1 0 name spi0ckr typ e rw r e s e t00000000 sfr address: 0xa2 table 23.4. spi0ckr register bit descriptions bit name function 7:0 spi0ckr spi0 clock rate. these bits determine the frequency of the sck o utput when the spi0 module is config - ured for master mode operation. the sck clock frequency is a divided version of the sys tem clock , and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 f sck sysclk 2 spi0ckr 1 + ?? ? ----------------------------------------------- =
c8051f85x/86x preliminary rev 0.6 227 serial peripheral interface (spi0) register 23.4. spi0dat: spi0 data bit 7 6 5 4 3 2 1 0 name spi0dat typ e rw r e s e t00000000 sfr address: 0xa3 table 23.5. spi0dat register bit descriptions bit name function 7:0 spi0dat spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0 - dat places the data into the transmit buffer and initiates a transfer when in master mode. a re ad of spi0 dat returns the contents of the receive buffer.
c8051f85x/86x preliminary rev 0.6 229 system management bus / i2c (smbus0) 24. system management bus / i 2 c (smbus0) the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, versi on 1.1, and compatible with the i 2 c serial bus. reads and writes to the smbu s by the system controller are byte oriented with the smbus interface autonomously controlling the serial transfer of the data. data can be transf erred at up to 1/20th of th e system clock as a master or slave (this can be faster than allowed by the smbus spec ification, depending on the sy stem clock used). a method of extending the clock-low duration is available to accommodate devices wit h different speed ca pabilities on the same bus. the smbus may operate as a master and/or slave, and ma y function on a bus with mu ltiple masters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and generation. the smbus peripher als can be fully driven by software (i.e., software accepts/rejects slave addresses, and generates acks), or hardware slave address re cognition and automatic ack generation can be enabled to minimize software overhead . a block diagram of the smbus0 peripheral is shown in figure 24.1. figure 24.1. smbus0 block diagram smbus0 slave address recognition smb0dat master scl clock generation shift register sda scl state control logic si timers 0, 1 or 2 scl low timer 3 data / address
c8051f85x/86x 230 preliminary rev 0.6 system management bus / i2c (smbus0) 24.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including sp ecifications), philips semiconductor. 2. the i 2 c-bus specificationversion 2.0, philips semiconductor. 3. system management bu s specificationversion 1. 1, sbs implementers forum. 24.2. smbus configuration figure 24.2 shows a typical smbus configuration. the smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. however, the maximum voltage on any port pin must conform to the electrical characteristics specific ations. the bi-directional scl (serial clock) and sda (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. every device connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by t he requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 24.2. typical smbus configuration 24.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addressed slave trans mitter to a master receiver (read). the master device initiates both types of data transfers and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master de vices on the same bus are supported. if two or more masters attempt to initia te a data transfer simultaneously, an arbitrat ion scheme is employed with a single master always winning the arbitration. it is not necessary to spec ify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start condit ion followed by an address byte (bits7C1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of dat a, and a stop condition. bytes that are received (by a master or slave) are acknowledged (ack) with a low sd a during a high scl (see figure 24.3). if the receiving device does not ack, the transmitting device will read a nack (not acknowledge), wh ich is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit posi tion of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl
c8051f85x/86x preliminary rev 0.6 231 system management bus / i2c (smbus0) all transactions are initiated by a ma ster, with one or more addressed slav e devices as the target. the master generates the start condition and then transmits the sl ave address and direction bit. if the transaction is a write operation from the master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operat ions, the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transactio n and free the bus. figure 24.3 illu strates a typical smbus transaction. figure 24.3. smbus transaction 24.3.1. transmitter vs. receiver on the smbus communications interface, a de vice is the transmitter when it is sending an address or data byte to another device on the bus. a device is a r eceiver when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda lin e during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, during which ti me the receiver controls the sda line. 24.3.2. arbitration a master may start a transfer only if the bus is free. the bus is fre e after a stop condition or after the scl and sda lines remain high for a specified ti me (see section 24.3.5. scl high (smb us free) timeout on page 232). in the event that two or more devices attempt to begin a transf er at the same time, an arbi tration scheme is employed to force one master to give up the bus. the master devi ces continue transmitting unt il one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. th e master attempting the high will detect a low sda and lose the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destructive: one devic e always wins, and no data is lost. 24.3.3. clock low extension smbus provides a clock synchronization mechanism, similar to i2c, which allows devices with different speed cap a bilities to coexist on th e bus. a clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. the slave ma y temporarily hold the scl line low to extend the clock low period, effectively decreasin g the serial clock frequency. 24.3.4. scl low timeout if the scl line is held low by a slave device on the bus, n o further communication is possible. furthermore, the master cannot force the scl line high to correct the erro r condition. to solve this problem, the smbus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition. devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. for the smbus0 interface, timer 3 is used to implement scl low timeouts. the scl low timeout feature is enabled by setting the smb0toe bit in smb0cf. the associated timer is forced to reload when scl is high, and allowed to count when scl is low. with the associated timer enab led and configured to overflow after 25 ms (and smb0toe set), the timer interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
c8051f85x/86x 232 preliminary rev 0.6 system management bus / i2c (smbus0) 24.3.5. scl high (smbus free) timeout the smbus specification stipul ates that if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the smb0fte bit in smb0cf is set, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master star t, the start will be generated following this timeout. a clock source is required for free timeout det ection, even in a slave-only implementation. 24.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. the smbus interface provides the following application-independent features: ?? byte-wise serial data transfers ?? clock signal generation on scl (master mode only) and sda data synchronization ?? timeout/bus error recognition, as defined by the smb0cf configuration register ?? start/stop timing, detection, and generation ?? bus arbitration ?? interrupt generation ?? status information ?? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave ad dress that is transferred. when hardware acknowledgement is disabled, the point at which the inte rrupt is generated depends on whether the hardware is acting as a data transmitter or receiver. when a transm itter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycl e so that software may read the rece ived ack value; when receiving data (i.e., receiving address/data, sending an ack), this interr upt is generated before the ack cycle so that software may define the outgoing ack value. if hardware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 24.5 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected). software sh ould read the smb0cn (smbus control register) to find the cause of the smbus interrupt. table 24.5 provides a quick smb0cn decoding reference. 24.4.1. smbus conf ig u ration register the smbus configuration register (smb0cf) is used to enab le the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and time out options. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus interface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will no t generate any slave interrupts. when the inh bit is set, all slave events will be inhibited following the next start (interrupts will c ontinue for the duration of the current transfer). table 24.1. smbus clock source selection smbcs smbus0 clock source 00 timer 0 overflow 01 timer 1 overflow 10 timer 2 high byte overflow 11 timer 2 low byte overflow
c8051f85x/86x preliminary rev 0.6 233 system management bus / i2c (smbus0) the smbcs bit field selects the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 24.1.the selected clock source may be shared by other peripherals so long as the timer is left running at all times. equation 24.1. minimum scl high and low times the selected clock source should be configured to est ablish the minimum scl high and low times as per equation 24.1. when the interface is operating as a mast er (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 24.2. equation 24.2. typical smbus bit rate figure 24.4 shows the typical scl generation described by equation 24.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other de vices on the bus (scl may be extended low by slower slave devices, or dr iven low by contending master devices). th e bit rate when oper ating as a master will never exceed the limits defined by equation equation 24.1. figure 24.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda lin e. the minimum sda setup time defines the absolute minimum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that th e current sda value remains st able after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 24.2 shows the minimum setup and hold times for the two exthold settings. setup and hold ti me extensions are typically necessary for smbus compliance when sysclk is above 10 mhz. table 24.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low C 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = scl ter source overflow scl h teout t low t h
c8051f85x/86x 234 preliminary rev 0.6 system management bus / i2c (smbus0) with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section 24.3.4. scl low timeou t on page 231). the smbus interfac e will force the associated timer to reload while scl is high, and allow the timer to count when scl is low. the timer interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detec tion can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 24.4). 24.4.2. smbus pin swap the smbus peripheral is assigned to pins using the priori ty crossb ar decoder. by default, the smbus signals are assigned to port pins starting with sda on the lower-nu mbered pin, and scl on the next available pin. the swap bit in the smbtc register can be set to 1 to reverse the order in which the smbus signals are assigned. 24.4.3. smbus timing control the sdd field in the smbtc register is used to restri ct the de tection of a start condition under certain circumstances. in some systems where there is significant mis-match between the impedance or the capacitance on the sda and scl lines, it may be possible for scl to fall after sda during an address or data transfer. such an event can cause a false start detection on the bus. these kind of events are not expected in a standard smbus or i2c-compliant system. in most systems this parameter should not be adjusted, and it is recommended that it be left at its default value. by default, if the scl falling edge is detected after the falling e dge of sda (i.e. one sysclk cycle or more), the device will detect this as a start condition. the sdd fiel d is used to increase the am ount of hold time that is required between sda and scl falling be fore a start is recognized. an addi tional 2, 4, or 8 sysclks can be added to prevent false start detection in systems where the bus conditions warrant this. 24.4.4. smb0cn co n trol register smb0cn is used to control the interface and to provid e status infor mation. the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave duri ng the current transfer. txmode indicates whether the device is transmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop has been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop c onditions when operating as a master. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is gener ated). writing a 1 to sto wh ile in master mode will cause the interface to generate a stop and end the current tran sfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occu r anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condition. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see table 24.3 for more details. important note about the si bit: the smbus interface is stalle d while si is set; thus scl is held low, and the bus is stalled until software clears si. note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgment, the s/ w delay occurs between the time smb0dat or ack is written and when si0 is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. table 24.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time
c8051f85x/86x preliminary rev 0.6 235 system management bus / i2c (smbus0) 24.4.4.1. software ack generation when the ehack bit in register smb0adm is cleared to 0, the firmware on th e device must detect incoming slave addresses and ack or nack the slave address and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ac k bit indicates the value received during the last ack cycle. ackrq is set each time a byte is received, indicati ng that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if software does not writ e the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; howeve r scl will remain low until si is cleare d. if a received slave address is not acknowledged, further slave events will be ignored unt il the next start is detected. 24.4.4.2. hardwa re ack generation when the ehack bit in register smb0adm is set to 1, automatic slave address recognition and ack generation is enabled. more detail about automatic slave address recognition can be found in section 24.4.5. as a receiver, the value currently specified by the ack bit will be automatica lly sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value rece ived on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further slave events will be ignore d until the next start is detected, and no interrupt will be generated. table 24.3 lists all sources for hardware changes to the smb0cn bits. refer to table 24.5 for smbus status decoding using the smb0cn register. table 24.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by ha rdware when: master ?? a start is generated. ?? a stop is generated. ?? arbitration is lost. txmode ?? start is generated. ?? smb0dat is written before the start of an smbus frame. ?? a start is detected. ?? arbitration is lost. ?? smb0dat is not written before the start of an smbus frame. sta ?? a start followed by an address byte is received. ?? must be cleared by software. sto ?? a stop is detected while addressed as a slave. ?? arbitration is lost due to a detected stop. ?? a pending stop is generated. ackrq ?? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ?? after each ack cycle. arblost ?? a repeated start is detected as a master when sta is low (unwanted repeated start). ?? scl is sensed low while attempting to generate a stop or repeated start condition. ?? sda is sensed low while transmitting a 1 (excluding ack bits). ?? each time sin is cleared. ack ?? the incoming ack value is low ? (acknowledge). ?? the incoming ack value is high (not acknowledge).
c8051f85x/86x 236 preliminary rev 0.6 system management bus / i2c (smbus0) 24.4.5. hardware slave address recognition the smbus hardware has the capabilit y to automatic ally recognize incomi ng slave addresses and send an ack without software intervention. automatic slave address recogn ition is enabled by setting the ehack bit in register smb0adm to 1. this will enable bo th automatic slave address recogn ition and automati c hardware ack generation for received bytes (as a master or slave). mo re detail on automatic hardware ack generation can be found in section 24.4.4.2. the registers used to define which address(es) are recognized by the hardware are the smbus slave address register and the smbus slave address mask register. a single address or range of addresses (including the general call address 0x00) can be specif ied using these two regist ers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in a bit of the slave address mask slvm enables a comparison between the received slave address and the hard wares slave address slv for that bit. a 0 in a bit of the slave address mask means that bit will be treated as a dont care for comparison purposes . in this case, either a 1 or a 0 value are acceptable on the incoming slave address . additionally, if the gc bi t in register smb0adr is set to 1, hardware will recognize the general call addr ess (0x00). table 24.4 show s some example parameter settings and the slave addresses that will be recognized by hard ware under thos e conditions. 24.4.6. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been r e ceived. software may safely read or write to the data regi ster when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shif ted out msb first. after a byte has been rece ived, the first bit of received data is located at the msb of smb0dat. while da ta is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. si ?? a start has been generated. ?? lost arbitration. ?? a byte has been transmitted and an ack/ nack received. ?? a byte has been received. ?? a start or repeated start followed by a slave address + r/w has been received. ?? a stop has been received. ?? must be cleared by software. table 24.4. hardware address recognition examples (ehack = 1) hardware slave address slv slave address mask slvm gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c table 24.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when:
c8051f85x/86x preliminary rev 0.6 237 system management bus / i2c (smbus0) 24.5. smbus transfer modes the smbus interface may be co nfigured to operate as mast er and/or slave. at any particular time, it will be operating in one of the following four modes: master trans mitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mode any ti me a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an sm bus interrupt is generated at the end of all smbus byte frames. the position of the ack interrupt when operat ing as a receiver depends on whether hardware ack generation is enabled. as a receiver, the interrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. as a transmitter, interrupts occur after the ack, regardless of whether hard ware ack generation is enabled or not. 24.5.1. write se que nce (master) during a write sequence, an smbus mast er writes data to a slave device. t he master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface generates the start condition and transmits the first byte containing the a ddress of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 0 (write). the master then transmits on e or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended when the sto bit is set and a stop is generat ed. the interface will switch to master receiver mode if smb0dat is not written following a master transmitter interrupt. figure 24 .5 shows a typical master write sequence. two transmit data bytes are shown, though any number of bytes may be tran smitted. notice that all of the data byte transferred interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 24.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f85x/86x 238 preliminary rev 0.6 system management bus / i2c (smbus0) 24.5.2. read sequence (master) during a read sequence, an smbus mast er reads data from a slave device. the master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. the smbus interface generates the start condition and transmits the first byte containing the a ddress of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 1 (read). serial data is then rece ived from the slave on sda while the smbus outputs the serial clock. the slav e transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must write the ack bit at that time to ack or nack the received byte. with hardware ack generation enable d, the smbus hard ware will automatically gene rate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the interfac e will switch to master transmitter m ode if smb0dat is written while an active master receiver. figure 24.6 shows a typical mast er read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the data byte transferred interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 24.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f85x/86x preliminary rev 0.6 239 system management bus / i2c (smbus0) 24.5.3. write sequence (slave) during a write sequence, an smbus ma st er writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during a ll data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start fo llowed by a slave address and direction bit (write in this case) is received. if hardware ack generation is disa bled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave ad dress with a nack. if hardware ack genera tion is enabled, the hardware will apply the ack for a slave address which ma tches the criteria set up by smb0 adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignor ed (by software or hardwar e), slave interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must write the ack bit at that time to ack or nack the received byte. with hardware ack generation enable d, the smbus hard ware will automatically gene rate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave receiver mo de after receiving a stop. the interf ace will switch to slave transmitter mode if smb0dat is written while an active slave receiver. figure 24.7 show s a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice that the data byte transferred interrupts occur at different places in th e sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 24.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f85x/86x 240 preliminary rev 0.6 system management bus / i2c (smbus0) 24.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads dat a from a slave device. the slave in this transfer will be a receiver during the address byte, and a transmitter during a ll data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receiv e the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, the hardware will apply the ack for a slave address wh ich matches the criteria set up by smb0adr and smb0adm. the interr upt will occur after the ack cycle. if the received slave address is ignor ed (by software or hardwar e), slave interrupts will be inhibited until the next start is detected. if the received slave address is acknowle dged, zero or more data bytes are transmitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and transmits one or more by tes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowledge bit is a nack, smb0dat should not be writ ten to before si is cleared (an error condition may be generated if smb0dat is wri tten following a received nack while in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. the interface will switch to slav e receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 24.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be tran smitted. notice that all of the data byte transferred interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 24.8. typical slave read sequence 24.6. smbus status decoding the current smbus status can be easily decoded using th e smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardwa re slave address recognition and ack generation is enabled or disabled. table 24.5 describes the typical ac tions when hardware slave address recognition and ack generation is disabled. table 24.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, txmode, sta, and sto. the shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the sm bus specification. highlighted responses are allowed by hardware but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f85x/86x preliminary rev 0.6 241 system management bus / i2c (smbus0) table 24.5. smbus status decoding: hardware ack disabled (ehack = 0) mode values read current smbus state typical response options values to wr i te next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 1100 000 a maste r data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 0 1 x 001 a ma ste r data or address byte was transmitted; ack received. load next data byte into smb0- dat. 0 0 x 1100 end transfer with stop. 0 1 x end transfer with stop and start an ot her transfer. 1 1 x send repeated start. 1 0 x 1110 switch to master receiver mode ( c lear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi ca te last byte, and send stop. 0 1 0 send nack to indi cate last byte, and send stop followed by start. 1 1 0 1110 send ack followed by repeated st ar t. 1 0 1 1110 send nack to indi cate last byte, and send repeated start. 1 0 0 1110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
c8051f85x/86x 242 preliminary rev 0.6 system management bus / i2c (smbus0) slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was tr ansmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave by te was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x a n illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 0 0 x slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with d a ta byte; ack received address 0 0 1 0100 nack received address. 0 0 0 11x l o st arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with da ta byte; ack received address 0 0 1 0100 nack received address. 0 0 0 reschedule failed transfer; nack received addres s. 1 0 0 11 10 0001 00 x a st op was detected while addressed as a slave transmitter or slave receiver. clear sto. 0 0 x 11x lost a r bitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 0000 1 0 x a slave byte was r eceived; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 bus error condition 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 1110 0001 0 1 x l o st arbitration due to a detected stop. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while trans mitting a data byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 1110 table 24.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f85x/86x preliminary rev 0.6 243 system management bus / i2c (smbus0) table 24.6. smbus status decoding: hardware ack enabled (ehack = 1) mode values read current smbus state typical response options values to wr i te next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0dat. 0 0 x 1100 1100 000 a ma ste r data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 0 1 x 001 a ma ste r data or address byte was transmitted; ack received. load next data byte into smb0- dat. 0 0 x 1100 end transfer with stop. 0 1 x end transfer with stop and start an ot her transfer. 1 1 x send repeated start. 1 0 x 1110 switch to master receiver mode ( c lear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data by te as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a ma ste r data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 read smb0dat; send stop follo wed by st art. 1 1 0 1110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100
c8051f85x/86x 244 preliminary rev 0.6 system management bus / i2c (smbus0) slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was tr ansmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave b y te was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x a n illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 0 0 x slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with da t a byte 0 0 x 0100 01x l o st arbitration as master; slave address + r/w rece ived; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with da t a byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00 x a stop was detected while addressed as a slave transmitter or slave receiver. clear sto. 0 0 x 01x lost ar bitration while attempting a stop. no action required (transfer complete/aborted). 0 0 0 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0da t . 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempting a repeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 1110 0001 0 1 x l o st arbitration due to a detected stop. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while trans mitting a data byte as master. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 1110 table 24.6. smbus status decoding: hardware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f85x/86x preliminary rev 0.6 245 system management bus / i2c (smbus0) 24.7. i2c / smbus control registers register 24.1. smb0cf: smbus0 configuration bit 7 6 5 4 3 2 1 0 name ensmb inh busy exthold smbtoe smbfte smbcs ty pe rw rw r rw rw rw rw r e s e t00000000 sfr address: 0xc1 table 24.7. smb0cf register bit descriptions bit name function 7 ensmb smbus0 enable. this bit enables the smbus0 interface when set to 1. when enabled, the interface con - stantly monitors the sda and scl pins. 6 inh smbus0 slave inhibit. when this bit is set to logic 1, the smbus0 do es not generate an interrupt when slave events occur. this effectively removes the smbus0 slave from the bus. master mode interrupts are not affected. 5 busy smbus0 busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 whe n a stop or free-timeout is sensed. 4 exthold smbus0 setup and hold time extension enable. this bit controls the sda setup and hold times. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3 smbtoe smbus0 scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus0 forces timer 3 to re loa d while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only th e high byte of the timer is held in reload while scl is high. timer 3 should be programmed to gener ate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus0 communication. 2 smbfte smbus0 free timeout detection enable. when this bit is set to logic 1, the bus will be cons idered free if sc l and sda remain high for more than 10 smbus clock source periods. 1:0 smbcs smbus0 clock source selection. these two bits select the smbus0 clock sour ce, which is used to ge nerate the smbus0 bit rate. see the smbus clock timing section for additional details. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow
c8051f85x/86x 246 preliminary rev 0.6 system management bus / i2c (smbus0) register 24.2. smb0tc: smbus0 timing and pin control bit 7 6 5 4 3 2 1 0 name swap reserved sdd typ e rw r rw r e s e t00000000 sfr address: 0xac table 24.8. smb0tc register bit descriptions bit name function 7 swap smbus0 swap pins. this bit swaps the order of the smbus0 pins on the crossbar. 0: sda is mapped to the lower-numbered port pin, and scl is mapped to the higher- n u mbered port pin. 1: scl is mapped to the lower-numbered port pin, and sda is mapped to the higher- numbered port pin. 6:2 reserved must write reset value. 1:0 sdd smbus0 start detection window. these bits increase the hold time requirement between sda falling and scl falling for start detection. 00: no additional hold time wi ndow (0-1 sysclk). 01: increase hold time window to 2-3 sysclks. 10: increase hold time window to 4-5 sysclks. 1 1: increase hold time window to 8-9 sysclks.
c8051f85x/86x preliminary rev 0.6 247 system management bus / i2c (smbus0) register 24.3. smb0cn: smbus0 control bit 7 6 5 4 3 2 1 0 name master txmode sta sto ackrq arblost ack si ty pe r r rw rw r r rw rw r e s e t00000000 sfr address: 0xc0 (bit-addressable) table 24.9. smb0cn register bit descriptions bit name function 7 master smbus0 master/slave indicator. this read-only bit indicates when the smbus0 is operating as a master. 0: smbus0 operating in slave mode. 1: smbus0 operating in master mode. 6 txmode smbus0 transmit mode indicator. this read-only bit indicates when the smbus0 is operating as a transmitter. 0: smbus0 in receiver mode. 1: smbus0 in transmitter mode. 5 sta smbus0 start flag. when reading sta, a 1 indicates that a start or repeated start condition was detected on th e bu s. writing a 1 to the sta bit initiates a start or repeated start on the bus. 4 sto smbus0 stop flag. when reading sto, a 1 indicates that a stop condition was detected on the bus (in slave mo de ) or is pending (in master mode). when acting as a master, writing a 1 to the sto bit initiates a stop condition on the bus. this b it is cleared by hardware. 3 ackrq smbus0 acknowledge request. 0: no ack requested. 1: ack requested. 2 arblost smbus0 arbitration lost indicator. 0: no arbitration error. 1: arbitration error occurred. 1 ack smbus0 acknowledge. when read as a master, the ack bit indica tes whethe r an ack (1) or nack (0) is received during the most recent byte transfer. as a slave, this bit should be written to send an ack (1) or nack (0) to a master requ est. note that the logic level of the ack bit on the smbus interface is inverted from the logic of the register ack bit.
c8051f85x/86x 248 preliminary rev 0.6 system management bus / i2c (smbus0) 0 si smbus0 interrupt flag. this bit is set by hardware to indicate that the current smbus0 state machine operation (s uch as writing a data or address byte) is co mplete. while si is se t, scl0 is held low and smbus0 is stalled. si0 must be cleared by software. clearing si0 initiates the next smbus0 state machine operation. table 24.9. smb0cn register bit descriptions bit name function
c8051f85x/86x preliminary rev 0.6 249 system management bus / i2c (smbus0) register 24.4. smb0adr: smbus0 slave address bit 7 6 5 4 3 2 1 0 name slv gc typ e rw rw r e s e t00000000 sfr address: 0xd7 table 24.10. smb0adr register bit descriptions bit name function 7:1 slv smbus hardware slave address. defines the smbus0 slave address(es) for au to matic ha rdware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm are checked against the incoming address. this allows multiple addresses to be recognized. 0 gc general call address enable. when hardware address recogn ition is enabled (ehac k = 1), this bit will determine whether the general call address (0x00) is also recognized by hardware. 0: general call address is ignored. 1: general call address is recognized.
c8051f85x/86x 250 preliminary rev 0.6 system management bus / i2c (smbus0) register 24.5. smb0adm: smbus0 slave address mask bit 7 6 5 4 3 2 1 0 name slvm ehack typ e rw rw r e s e t11111110 sfr address: 0xd6 table 24.11. smb0adm register bit descriptions bit name function 7:1 slvm smbus0 slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, a nd which b its are ignored. any bit set to 1 in slvm enables comparisons with the corre - sponding bit in slv. bits set to 0 are ignored (can be either 0 or 1 in the incoming a ddr ess). 0 ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled.
c8051f85x/86x preliminary rev 0.6 251 system management bus / i2c (smbus0) register 24.6. smb0dat: smbus0 data bit 7 6 5 4 3 2 1 0 name smb0dat typ e rw r e s e t00000000 sfr address: 0xc2 table 24.12. smb0dat register bit descriptions bit name function 7:0 smb0dat smbus0 data. the smb0dat register contains a byte of dat a to be transmitted on the smbus0 serial interface or a byte that has just been receiv ed on the smbus0 serial interface. the cpu can safely read from or write to this register whenever the si serial interrupt flag is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this register.
c8051f85x/86x 252 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) 25. timers (timer0, timer1, timer2 and timer3) each mcu in the c8051f85x/86x family includes four coun ter/timers: two are 16-bit c ounter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timers for timing peripherals or for general purpose use. these timers can be used to measure time intervals, count ex ternal events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identi cal and have four primary modes of operation. timer 2 and timer 3 are also identical and offer bo th 16-bit and split 8-bit timer functionality wit h auto-reload capabilities. timer 2 and timer 3 both offer a capture function, but ar e different in their system-lev el connections. timer 2 is capable of performing a capture function on an external signal input routed through the crossbar, while the timer 3 capture is dedicated to the lo w-frequency oscillator output. table 25.1 summarizes the modes available to each timer. timers 0 and 1 may be clocked by one of five sour ces, d e termined by the timer mode select bits (t1m C t0m) and the clock scale bits (sca1 C sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked. timer 0/1 may then be configured to use this pre-scaled cl ock signal or the system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a frequency of up to one-fourth the system clock frequency can be counted. the i nput signal need not be periodic, but it must be held at a given level for at least two full system clock c ycles to ensure the leve l is properly sampled. all four timers are capable of clocking other peripherals and triggering events in the system. the individual peripherals select which timer to use for their respec tive functions. table 25.2 summarizes the peripheral connections for each timer. note that the timer 2 and timer 3 high overflows apply to the full timer when operating in 16-bit mode or the high-byte timer when operating in 8-bit split mode. table 25.1. timer modes timer 0 and timer 1 modes timer 2 modes timer 3 modes 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer two 8-bit timers with auto-reload two 8-bit timers with auto-reload 8-bit counter/timer wit h auto-reload input pin capture l ow-frequency oscillator capture two 8-bit counter/timers (timer 0 only) table 25.2. timer peripheral clocking / event triggering function t0 overf low t1 overflow t 2 high overflow t2 low overflow t3 high over flow t3 low overf low uart0 baud rate x smbus0 clock rate x x x x smbus0 scl low timeout x pca0 clock x adc0 conversion start x x* x* x* x* *note: the high-side overflow is used when the timer is in16-bit mode. the low-side overflow is used in 8-bit mode.
c8051f85x/86x preliminary rev 0.6 253 timers (timer0, timer1, timer2 and timer3) 25.1. timer 0 and timer 1 timer 0 and timer 1 are each implemented as a16-bit regist er accessed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer c ontrol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie register. timer 1 interrupts can be enabled by setting the et1 bit in the ie register. both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1 C t0m0 in the counter/timer mode register (tmod). each timer can be configured independently for the operating modes described below.
c8051f85x/86x 254 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) 25.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identic ally, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit count er/timer. tl0 holds the five lsbs in bit positions tl0.4 C tl0.0. the three upper bits of tl0 (tl0.7 C tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and over flows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 in terrupts are enabled. the ct0 bit in the tmod register selects the counter/timer' s clock source. when ct0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) incremen t the timer register. clearing ct selects the clock defined by the t0m bit in register ckcon. when t0m is set, timer 0 is clocked by th e system clock. when t0m is cleared, timer 0 is clocked by the source sele cted by the clock scale bits in ckcon. setting the tr0 bit enables the timer when either gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in0pl in register it01cf. setting gate0 to 1 allows the timer to be controlled by the external input signal int0 , facilitating pulse width measurements setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the /int1 polarity is defined by bit in1pl in register it01cf. figure 25.1. t0 mode 0 block diagram 25.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the counter/timers ar e enabled and configured in mode 1 in the same manner as for mode 0. tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care tclk tr0 0 1 0 1 sysclk pre-scaled clock gate0 in0pl xor t0m t0 int0 ct0 tl0 (5 bits) th0 (8 bits) tf0 (interrupt flag)
c8051f85x/86x preliminary rev 0.6 255 timers (timer0, timer1, timer2 and timer3) 25.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload value. when the counter in tl0 overflows from all ones to 0x00, the timer overflow flag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interrupt will occur when the tf0 flag is set. the reload value in th 0 is not c hanged. tl0 must be initialized to the desired value before enabling t he timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit enables the timer when either gate0 in the tmod re gister is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it01cf. figure 25.2. t0 mode 2 block diagram reload tl0 (8 bits) th0 (8 bits) tf0 (interrupt flag) tclk tr0 0 1 0 1 sysclk pre-scaled clock gate0 in0pl xor t0m t0 int0 ct0
c8051f85x/86x 256 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) 25.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit coun ter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 c ontrol/status bits in tcon and tmod : tr0, ct0, gate0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled usin g the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf 1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbu s and/or uart, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 25.3. t0 mode 3 block diagram tclk tr0 0 1 0 1 sysclk pre-scaled clock gate0 in0pl xor t0m t0 int0 ct0 tr1 tl0 (8 bits) tf0 (interrupt flag) th0 (8 bits) tf1 (interrupt flag)
c8051f85x/86x preliminary rev 0.6 257 timers (timer0, timer1, timer2 and timer3) 25.2. timer 2 and timer 3 timer 2 and timer 3 are functionally equivalent, with the on ly differences being the top-level connections to other parts of the system, as detailed in table 25.1 and table 25.2. the timers are 16 bits wide, formed by two 8-bit sfrs: tmrnl (low byte) and tmrnh (high byte). each timer may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the tnsplit bit in tmrncn defines the timer operation mode. the timers may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. note that the external oscillator sour ce divided by 8 is synchronized with the system clock. 25.2.1. 16-bit time r w ith auto-reload when tnsplit is zero, the timer operates as a 16-bit ti mer with au to-reload. in this mode, the timer may be configured to clock from sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer reload registers (tmrnrlh and tmrnrll) is loaded into the main timer count register as shown in figure 25.4, and the high byte overflow flag (tfnh) is set. if the timer in terrupts are enabled, an inte rrupt will be generated on each timer overflow. additionally, if the timer interrupts ar e enabled and the tfnlen bit is set, an interrupt will be generated each time the lower 8 bits (tmrnl) overflow from 0xff to 0x00. figure 25.4. 16-bit mode block diagram extclk / 8 sysclk / 12 sysclk tmrnl tmrnh reload tclk 0 1 trn 0 1 tnxclk interrupt tfnl overflow tfnh overflow tnml tmrnrll tmrnrlh tfnlen
c8051f85x/86x 258 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) 25.2.2. 8-bit timers with auto-reload when tnsplit is set, the timer operates a s two 8-bit timers (tmrnh and tmrnl). both 8-bit timers operate in auto-reload mode as shown in figure 25.5. tmrnrll holds the reload value for tmrnl; tmrnrlh holds the reload value for tmrnh. the trn bit in tmrncn handles the run control for tmrnh. tmrnl is always running when configured for 8-bit auto-reload mode. each 8-bit timer may be configured to clock from sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the clock select bits (tnmh and tnml in ckcon) select either sysclk or the clock defined by the external clock select bit (tnxclk in tmrncn), as follows: the tfnh bit is set when tmrnh overfl ows from 0xff to 0x00; the tfnl bit is set when tmrnl overflows from 0xff to 0x00. when timer interrupts are enabled, an interrupt is generated each time tmrnh overflows. if tmier interrupts are enabled and tfnlen is set, an interrupt is generated each time either tmrnl or tmrnh overflows. when tfnlen is enabled, software must check the tfnh and tfnl flags to determine the source of the timer interrupt. the tfnh and tfnl interrupt flags are not cl eared by hardware and must be manually cleared by software. figure 25.5. 8-bit mode block diagram tnmh tnxclk tmrnh clock source tnml tnxclk tmrnl clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk tclk 0 1 trn external clock / 8 sysclk / 12 0 1 tnxclk 1 0 tmrnh tmrnrlh reload reload tclk tmrnrll interrupt tfnl overflow tfnlen sysclk tmrnl tfnh overflow tnml tnmh
c8051f85x/86x preliminary rev 0.6 259 timers (timer0, timer1, timer2 and timer3) 25.2.3. capture mode capture mode allows an external input (timer 2) or the low-frequency oscillato r clock (timer 3) to be measured against the system clock or an external oscillator source. the timer ca n be clocked from the system clock, the system clock divided by 12, or the external oscillator di vided by 8, depend ing on the tnml, and tnxclk settings. setting tfncen to 1 enables capture mode. in this mode, tnsplit should be set to 0, as the full 16-bit timer is used. upon a falling edge of the input capture signal, the contents of the timer regist er (tmrnh:tmrnl) are loaded into the reload registers (tmrnrlh:tmrnrll) and the tfnh flag is set. by recording the difference between two successive timer capture values, the perio d of the captured signal can be determined with respect to the selected timer clock. figure 25.6. capture mode block diagram external clock / 8 sysclk / 12 sysclk 0 1 0 1 tnxclk tmrnl tmrnh tclk trn tmrnrll tmrnrlh capture t2 pin (timer 2) l-f oscillator (timer 3) tfncen tnml tfnh (interrupt)
c8051f85x/86x 260 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) 25.3. timer control registers register 25.1. ckcon: clock control bit 7 6 5 4 3 2 1 0 name t3mh t3ml t2mh t2ml t1m t0m sca ty pe rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0x8e table 25.3. ckcon register bit descriptions bit name function 7 t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6 t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. select s the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5 t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4 t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit sel ects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3 t1m timer 1 clock select. selects the clock source su pp lie d to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale field, sca. 1: timer 1 uses the system clock. 2 t0m timer 0 clock select. selects the clock source su pp lie d to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defined by the prescale field, sca. 1: counter/timer 0 uses the system clock.
c8051f85x/86x preliminary rev 0.6 261 timers (timer0, timer1, timer2 and timer3) 1:0 sca timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (s yn ch ronized with the system clock) table 25.3. ckcon register bit descriptions bit name function
c8051f85x/86x 262 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.2. tcon: timer 0/1 control bit 7 6 5 4 3 2 1 0 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 ty pe rw rw rw rw rw rw rw rw r e s e t00000000 sfr address: 0x88 (bit-addressable) table 25.4. tcon register bit descriptions bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. th is flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6 tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. th is flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4 tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3 ie1 external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can b e cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2 it1 interrupt 1 type select. this bit selects whether the conf igured in t1 interrup t w ill be edge or level sensitive. int1 is configured active low or high by the in1pl bit in register it01cf. 0: int1 is level triggered. 1: int1 is edge triggered. 1 ie0 external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can b e cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0 it0 interrupt 0 type select. this bit selects whether the conf igured in t0 interrup t w ill be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf. 0: int0 is level triggered. 1: int0 is edge triggered.
c8051f85x/86x preliminary rev 0.6 263 timers (timer0, timer1, timer2 and timer3) register 25.3. tmod: timer 0/1 mode bit 7 6 5 4 3 2 1 0 name gate1 ct1 t1m gate0 ct0 t0m ty pe rw rw rw rw rw rw r e s e t00000000 sfr address: 0x89 table 25.5. tmod register bit descriptions bit name function 7 gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in reg - ister it01cf. 6 ct1 counter/timer 1 select. 0: timer mode. timer 1 increments on the clock defined by t1m in the ckcon register. 1: counter mode. timer 1 increments on high-t o - low transitions of an external pin (t1). 5:4 t1m timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3 gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in reg - ister it01cf. 2 ct0 counter/timer 0 select. 0: timer mode. timer 0 increments on the clock defined by t0m in the ckcon register. 1: counter mode. timer 0 increments on high-t o - low transitions of an external pin (t0). 1:0 t0m timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers
c8051f85x/86x 264 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.4. tl0: timer 0 low byte bit 7 6 5 4 3 2 1 0 name tl0 typ e rw r e s e t00000000 sfr address: 0x8a table 25.6. tl0 register bit descriptions bit name function 7:0 tl0 timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0.
c8051f85x/86x preliminary rev 0.6 265 timers (timer0, timer1, timer2 and timer3) register 25.5. tl1: timer 1 low byte bit 7 6 5 4 3 2 1 0 name tl1 typ e rw r e s e t00000000 sfr address: 0x8b table 25.7. tl1 register bit descriptions bit name function 7:0 tl1 timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1.
c8051f85x/86x 266 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.6. th0: timer 0 high byte bit 7 6 5 4 3 2 1 0 name th0 typ e rw r e s e t00000000 sfr address: 0x8c table 25.8. th0 register bit descriptions bit name function 7:0 th0 timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0.
c8051f85x/86x preliminary rev 0.6 267 timers (timer0, timer1, timer2 and timer3) register 25.7. th1: timer 1 high byte bit 7 6 5 4 3 2 1 0 name th1 typ e rw r e s e t00000000 sfr address: 0x8d table 25.9. th1 register bit descriptions bit name function 7:0 th1 timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1.
c8051f85x/86x 268 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.8. tmr2cn: timer 2 control bit 7 6 5 4 3 2 1 0 name tf2h tf2l tf2len tf2cen t2split tr2 reserved t2xclk ty pe rw rw rw rw rw rw r rw r e s e t00000000 sfr address: 0xc8 (bit-addressable) table 25.10. tmr2cn register bit descriptions bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when t imer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes th e cpu to vector to th e timer 2 interrupt ser - vice routine. this bit is not au toma tically clear ed by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the t i mer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automat - ically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 low by te interrupt s. if timer 2 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 2 overflows. 4 tf2cen timer 2 capture enable. when set to 1, this bit enables timer 2 ca ptur e mode. if tf2cen is set and timer 2 interrupts are enab led, an interrupt will be generated on a falling edge of the selected t2 input pin, and the cu rrent 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2rll. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. 2 tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-b i t mode, this bit enables/disables tmr2h only; tmr2l is always enabled in split mode. 1 reserved must write reset value. 0 t2xclk timer 2 external clock select. this bit selects the external clock source for t imer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clock divided by 8 (synchronized with sysclk).
c8051f85x/86x preliminary rev 0.6 269 timers (timer0, timer1, timer2 and timer3) register 25.9. tmr2rll: timer 2 reload low byte bit 7 6 5 4 3 2 1 0 name tmr2rll typ e rw r e s e t00000000 sfr address: 0xca table 25.11. tmr2rll register bit descriptions bit name function 7:0 tmr2rll timer 2 reload low byte. when operating in one of the auto-reload mod e s, tmr2rll holds the reload value for the low byte of timer 2 (tmr2l). when oeprating in capture mode, tmr2rll is the cap - tured value of tmr2l.
c8051f85x/86x 270 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.10. tmr2rlh: timer 2 reload high byte bit 7 6 5 4 3 2 1 0 name tmr2rlh typ e rw r e s e t00000000 sfr address: 0xcb table 25.12. tmr2rlh register bit descriptions bit name function 7:0 tmr2rlh timer 2 reload high byte. when operating in one of the auto-reload modes, tmr2rlh holds the reload value for the high byte of timer 2 (tmr2h). when oeprating in capture mode, tmr2rlh is the captured value of tmr2h.
c8051f85x/86x preliminary rev 0.6 271 timers (timer0, timer1, timer2 and timer3) register 25.11. tmr2l: timer 2 low byte bit 7 6 5 4 3 2 1 0 name tmr2l typ e rw r e s e t00000000 sfr address: 0xcc table 25.13. tmr2l register bit descriptions bit name function 7:0 tmr2l timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit m o de, tmr2l contains the 8-bit low byte timer value.
c8051f85x/86x 272 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.12. tmr2h: timer 2 high byte bit 7 6 5 4 3 2 1 0 name tmr2h typ e rw r e s e t00000000 sfr address: 0xcd table 25.14. tmr2h register bit descriptions bit name function 7:0 tmr2h timer 2 high byte. in 16-bit mode, the tmr2h register contains t he hig h byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value.
c8051f85x/86x preliminary rev 0.6 273 timers (timer0, timer1, timer2 and timer3) register 25.13. tmr3cn: timer 3 control bit 7 6 5 4 3 2 1 0 name tf3h tf3l tf3len tf3cen t3split tr3 reserved t3xclk ty pe rw rw rw rw rw rw r rw r e s e t00000000 sfr address: 0x91 table 25.15. tmr3cn register bit descriptions bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when t imer 3 overflows from 0x ffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes th e cpu to vector to th e timer 3 interrupt ser - vice routine. this bit is not au toma tically clear ed by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the t i mer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not automat - ically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 low by te interrupt s. if timer 3 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 3 overflows. 4 tf3cen timer 3 capture enable. when set to 1, this bit enables timer 3 ca ptur e mode. if tf3cen is set and timer 3 interrupts are enabled, an inte rrupt will be generated on a falling edge of the low-fre - quency oscillator output, and the current 16-bit timer valu e in tmr3h:tmr3l w ill be cop - ied to tmr3rlh:tmr3rll. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bit auto-reload timers. 2 tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-b i t mode, this bit enables/disables tmr3h only; tmr3l is always enabled in split mode. 1 reserved must write reset value. 0 t3xclk timer 3 external clock select. this bit selects the external clock source for t imer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock source for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 clock is the system clock divided by 12. 1: timer 3 clock is the external clock divided by 8 (synchronized with sysclk).
c8051f85x/86x 274 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.14. tmr3rll: timer 3 reload low byte bit 7 6 5 4 3 2 1 0 name tmr3rll typ e rw r e s e t00000000 sfr address: 0x92 table 25.16. tmr3rll register bit descriptions bit name function 7:0 tmr3rll timer 3 reload low byte. when operating in one of the auto-reload mod e s, tmr3rll holds the reload value for the low byte of timer 3 (tmr3l). when oeprating in capture mode, tmr3rll is the cap - tured value of tmr3l.
c8051f85x/86x preliminary rev 0.6 275 timers (timer0, timer1, timer2 and timer3) register 25.15. tmr3rlh: timer 3 reload high byte bit 7 6 5 4 3 2 1 0 name tmr3rlh typ e rw r e s e t00000000 sfr address: 0x93 table 25.17. tmr3rlh register bit descriptions bit name function 7:0 tmr3rlh timer 3 reload high byte. when operating in one of the auto-reload modes, tmr3rlh holds the reload value for the high byte of timer 3 (tmr3h). when oeprating in capture mode, tmr3rlh is the captured value of tmr3h.
c8051f85x/86x 276 preliminary rev 0.6 timers (timer0, timer1, timer2 and timer3) register 25.16. tmr3l: timer 3 low byte bit 7 6 5 4 3 2 1 0 name tmr3l typ e rw r e s e t00000000 sfr address: 0x94 table 25.18. tmr3l register bit descriptions bit name function 7:0 tmr3l timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit m o de, tmr3l contains the 8-bit low byte timer value.
c8051f85x/86x preliminary rev 0.6 277 timers (timer0, timer1, timer2 and timer3) register 25.17. tmr3h: timer 3 high byte bit 7 6 5 4 3 2 1 0 name tmr3h typ e rw r e s e t00000000 sfr address: 0x95 table 25.19. tmr3h register bit descriptions bit name function 7:0 tmr3h timer 3 high byte. in 16-bit mode, the tmr3h register contains t he hig h byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value.
c8051f85x/86x 278 preliminary rev 0.6 universal asynchronous receiver/transmitter (uart0) 26. universal asynchronous receiver/transmitter (uart0) uart0 is an asynchronous, full duplex serial port offe ring modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section 26.1. enhanced baud rate generation on page 278). rece ived data buffering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous data byte. uart0 has two associated sfrs: serial control register 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is comple ted (ti is set in scon0), or a data byte has been received (ri is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interrupt service routine. they must be cl eared manually by software, allowing soft- ware to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 26.1. uart0 block diagram 26.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit au to-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl 1 (shown as rx timer in figure 26.2), wh ich is not user-accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. uart0 sbuf (8 lsbs) input shift register rx baud rate generator (timer 1) start detection output shift register tx tb8 (9 th bit) rb8 (9 th bit) control / configuration ti, ri interrupts tx clk rx clk
c8051f85x/86x preliminary rev 0.6 279 universal asynchronous r eceiver/transmitter (uart0) figure 26.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload. the timer 1 reload value should be set so that overflows will occur at two times the desi red uart baud rate frequency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysc lk/12, sysclk/48, the exte rnal oscillator clock/8, or an external input t1. for any given timer 1 overflow rate, the uart0 baud rate is determined by equation 26.1. equation 26.1. uart0 baud rate timer 1 overflow rate is selected as described in the timer section. a quick reference for typical baud rates and system clock frequencies is given in table 26.1. start detection tx clock 2 rx clock 2 tl1 th1 rx timer baud rate generator (in timer 1) uartbaudrate 1 2 -- - t1_overflow_rate ? =
c8051f85x/86x 280 preliminary rev 0.6 universal asynchronous receiver/transmitter (uart0) 26.2. operational modes uart0 provides standard asynchronous, full duplex communicati on. the uart mode (8-bit or 9-bit) is selected by the s0mode bit in register scon. 26.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. da t a are transmitted lsb first from the tx pin and received at the rx pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb8 in the scon register. data transmission begins when software writes a data byte to the sbuf0 register. the ti transmit interrupt flag is set at the end of the transmission (the beginning of the stop -bit time). data reception can begin any time after the ren receive enable bit is set to logic 1. after the stop bi t is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: ri must be logic 0, and if mce is logic 1, the stop bit must be logic 1. in the event of a receive data overrun, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb8 and the ri flag is set. if these conditions are not met, sbuf0 and rb8 will not be loaded and the ri flag will not be set. an interrupt will occur if enabled when either ti or ri is set. figure 26.3. 8-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
c8051f85x/86x preliminary rev 0.6 281 universal asynchronous r eceiver/transmitter (uart0) 26.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data by te: a st art bit, 8 data bits (lsb first), a programmable ninth data bit, and a stop bit. the state of the ninth transmit data bit is determined by the val ue in tb8, which is assigned by user software. it can be assigned the value of the parity flag (bit p in register psw) for error detection, or used in multiprocessor comm unications. on receive, the ninth data bit goes into rb8 and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti transmit interrupt flag is set at the end of the transmission (the beginning of the stop-bit time). data reception can begin any time after the ren receive enable bit is se t to 1. after the stop bit is received , the data byte will be loaded into the sbuf0 receive register if the following conditions are met: (1 ) ri must be logic 0, and (2 ) if mce is logic 1, the 9th bit must be logic 1 (when mce is logic 0, the state of the ninth data bit is unimportant). if these conditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb8, and the ri flag is set to 1. if the above conditions are not met, sbuf0 and rb 8 will not be loaded and the ri flag will no t be set to 1. a uart0 interrupt will occur if enabled when either ti or ri is set to 1. figure 26.4. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
c8051f85x/86x 282 preliminary rev 0.6 universal asynchronous receiver/transmitter (uart0) 26.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a ma ster processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an add ress byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce bit of a slave processor configures its ua rt such that when a stop bit is received, the uart will generate an interrupt only if the ninth bit is logic 1 (rb8 = 1) signifying an address byte has been received. in the uart interrupt handler, software will compare the received addr ess with the slave's own a ssigned 8-bit address. if the addresses match, the slave will clear its mce bit to e nable interrupts on the rec eption of the following data byte(s). slaves that weren't address ed leave their mce bits set and do not gen erate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce bit to ignore all transmissions until it receives the next address byte. multiple addresses can be assigned to a single slave and/ or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissions or a protocol ca n be implemented such that the master/slave role is temporarily reversed to enable half-duplex transm ission between the original master and slave(s). figure 26.5. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f85x/86x preliminary rev 0.6 283 universal asynchronous r eceiver/transmitter (uart0) table 26.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator frequency: 49 mhz target baud rate (b p s) baud rate % error oscillator divide fac t or timer clock source sca1Csca0 (pre-scale se le ct) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 C0.32% 106 sysclk xx 2 1 0xcb 115200 C0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 C0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 C0.32% 2544 sysclk/12 00 0 0x96 2400 C0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 C sca0 and t1m bit definitions can be found in timer1 chapter. 2. x = dont care.
c8051f85x/86x 284 preliminary rev 0.6 universal asynchronous receiver/transmitter (uart0) 26.4. uart control registers register 26.1. scon0: uart0 serial port control bit 7 6 5 4 3 2 1 0 name smode reserved mce ren tb8 rb8 ti ri ty perw r rwrwrwrwrwrw r e s e t01000000 sfr address: 0x98 (bit-addressable) table 26.2. scon0 register bit descriptions bit name function 7 smode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate (mode 0). 1: 9-bit uart with variable baud rate (mode 1). 6 reserved must write reset value. 5 mce multiprocessor communication enable. this bit enables checking of the stop bit or th e 9 th bit in multi-drop communication buses. the function of this bit is dependent on the uart0 operation mode selected by the smode bit. in mode 0 (8-bits), the peripheral will check that the stop bit is logic 1. in mode 1 (9-bits) the peripheral will ch eck for a logic 1 on the 9th bit. 0: ignore level of 9th bit / stop bit. 1: ri is set and an interrupt is generated only when the stop bit is logic 1 (mode 0) or whe n the 9th bit is logic 1 (mode 1). 4 ren receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3 tb8 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bit in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2 rb8 ninth receive bit. rb8 is assigned the value of the stop bit in mod e 0; it is assigned the value of the 9th data bit in mode 1. 1 ti transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8 - bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit ca uses the cpu to vector to the uart0 inter - rupt service routine. this bit must be clea red manually by software.
c8051f85x/86x preliminary rev 0.6 285 universal asynchronous r eceiver/transmitter (uart0) 0 ri receive interrupt flag. set to 1 by hardware when a byte of data has bee n received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software. table 26.2. scon0 register bit descriptions bit name function
c8051f85x/86x 286 preliminary rev 0.6 universal asynchronous receiver/transmitter (uart0) register 26.2. sbuf0: uart0 serial port data buffer bit 7 6 5 4 3 2 1 0 name sbuf0 typ e rw r e s e t00000000 sfr address: 0x99 table 26.3. sbuf0 register bit descriptions bit name function 7:0 sbuf0 serial data buffer bits. this sfr accesses two registers; a transmit sh if t register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 in itiates the transmission. a read of sbuf0 returns the contents of the receive latch.
c8051f85x/86x 288 preliminary rev 0.6 watchdog timer (wdt0) 27. watchdog timer (wdt0) the c8051f85x/86x family includes a programmable watchdog timer (wdt) running off the low-frequency oscillator. a wdt overflow will force the mcu into the reset state. to prevent the reset, the wdt must be restarted by application software before overflow. if the system ex periences a software or hardware malfunction preventing the software from restar ting the wdt, the wdt will overflow and cause a reset. following a reset the wdt is automatically enabled and runn ing with the default maximum time interval. if desired the wdt can be disabled by system software or locked on to prevent accidental disabling. once locked, the wdt cannot be disabled until the next system reset. the state of the rst pin is unaffected by this reset. the wdt consists of an intern al timer running from the low-frequency oscillator. the timer measures the period between specific writes to its cont rol register. if this period exceeds the programmed limit, a wdt reset is generated. the wdt can be enabled and disabled as ne eded in software, or can be permanently enabled if desired. when the wdt is active, the lo w-frequency oscillator is fo rced on. all watchdog fe atures are controlled via the watchdog timer control register (wdtcn). figure 27.1. watchdog timer block diagram watchdog timer lfosc0 watchdog timer lock and key watchdog reset timeout interval
c8051f85x/86x preliminary rev 0.6 289 watchdog timer (wdt0) 27.1. enabling / resetting the wdt the watchdog timer is both enabled and reset by writin g 0xa5 to the wdtcn regist er. the user's application software should include periodic writ es of 0xa5 to wdtcn as needed to prevent a watchdog timer overflow. the wdt is enabled and reset as a result of any system reset. 27.2. disabling the wdt writing 0xde followed by 0xad to the wdtcn register disables the wdt. the following code segment illustrates disabling the wdt: clr ea ; disable all interrupts mov wdtcn,#0deh ; disable software watchdog timer mov wdtcn,#0adh setb ea ; re-enable interrupts the writes of 0xde and 0xad must occur within 4 clock cyc les of each other, or the disable operation is ignored. interrupts should be disabled during this procedure to avoid delay between the two writes. 27.3. disabling the wdt lockout writing 0xff to wdtcn locks out the disable feature. on ce locked out, the disable operation is ignored until the next system reset. writing 0xff does not enable or reset the watchdog timer. applications always intending to use the watchdog should write 0xff to wdtcn in the initialization code. 27.4. setting the wdt interval wdtcn.[2:0] controls the watchdog timeout interval. the interval is given by the following equation, where t lfosc is the low-frequency oscillator clock period: this provides a nominal interval range of 0.8 ms to 13.1 s. wdtcn.7 must be logic 0 when setting this interval. read ing wdtcn returns the programmed interval. wdtcn.[2:0] reads 111b after a system reset. t lfosc 4 wdtcn[2:0] 3 +
c8051f85x/86x 290 preliminary rev 0.6 watchdog timer (wdt0) 27.5. watchdog timer control registers register 27.1. wdtcn: watchdog timer control bit 7 6 5 4 3 2 1 0 name wdtcn typ e rw r e s e t00010111 sfr address: 0x97 table 27.1. wdtcn register bit descriptions bit name function 7:0 wdtcn wdt control. the wdt control field has different behavior for reads and writes. read: when reading the wdtcn register, the lower three bits (wdtcn[2:0]) indicate the cur - rent timeout interval. bit wdtcn.4 indicates wh et her the wdt is active (logic 1) or inac - tive (logic 0). write: writing the wdtcn register can set the timeou t in terval, enable the wdt, disable the wdt, reset the wdt, or lock the wdt to prevent disabling. writing to wdtcn with the msb (wdtcn.7) clea red to 0 will set the timeout interval to the value in bits wdtcn[2:0]. writing 0xa5 both enables and reloads the wdt. writing 0xde followed within 4 system clo c ks by 0xad disables the wdt. writing 0xff locks out the disable feature until the next device reset.
c8051f85x/86x 292 preliminary rev 0.6 c2 interface 28. c2 interface c8051f85x/86x devices include an on-c hip silicon labs 2-wire (c2) debug interf ace to allow fl ash programming and in-system debugging with the production part installed in the end application. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d ) to transfer information between the device and a host system. details on the c2 protocol can be found in the c2 interface specification. 28.1. c2 pin sharing the c2 protocol allows the c2 pins to be shared with user functions so that in-system debugging and flash programming may be performed. c2ck is shared with the rst pin, while the c2d signal is shared with a port i/o pin. this is possible because c2 communication is typica lly performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely borrow the c2ck and c2d pins. in most applications, external resistor s are required to isolate c2 interface traffic from the user application. a typical isolation c onfiguration is shown in figure 28.1. figure 28.1. typical c2 pin sharing the configuration in figure 28.1 assumes the following: 1. the user input (b) cannot change state while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx
c8051f85x/86x preliminary rev 0.6 293 c2 interface 28.2. c2 interface registers the following describes the c2 registers necessary to perf orm flash programming through the c2 interface. all c2 registers are accessed through the c2 interface, and are not available in the sfr map for firmware access. register 28.1. c2add: c2 address bit 7 6 5 4 3 2 1 0 name c2add typ e rw r e s e t00000000 this register is part of the c2 protocol. table 28.1. c2add register bit descriptions bit name function 7:0 c2add c2 address. the c2add register is accessed via the c2 inte rface. the valu e written to c2add selects the target data register for c2 data read and data write commands. 0x00: c2devid 0x01: c2revid 0x02: c2fpctl 0xb4: c2fpdat
c8051f85x/86x 294 preliminary rev 0.6 c2 interface register 28.2. c2devid: c2 device id bit 7 6 5 4 3 2 1 0 name c2devid typ e r r e s e t00110000 c2 address: 0x00 table 28.2. c2devid register bit descriptions bit name function 7:0 c2devid device id. this read-only register returns the 8 - bit device id: 0x30 (c8051f85x/86x).
c8051f85x/86x preliminary rev 0.6 295 c2 interface register 28.3. c2revid: c2 revision id bit 7 6 5 4 3 2 1 0 name c2revid typ e r r e s e txxxxxxxx c2 address: 0x01 table 28.3. c2revid register bit descriptions bit name function 7:0 c2revid revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a, 0 x 01 = revision b and 0x02 = revision c.
c8051f85x/86x 296 preliminary rev 0.6 c2 interface register 28.4. c2fpctl: c2 flash programming control bit 7 6 5 4 3 2 1 0 name c2fpctl typ e rw r e s e t00000000 c2 address: 0x02 table 28.4. c2fpctl register bit descriptions bit name function 7:0 c2fpctl flash programming control register. this register is used to enable flash progr amm i ng via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is enabled, a system reset must be issued to resume normal operation.
c8051f85x/86x preliminary rev 0.6 297 c2 interface register 28.5. c2fpdat: c2 flash programming data bit 7 6 5 4 3 2 1 0 name c2fpdat typ e rw r e s e t00000000 c2 address: 0xb4 table 28.5. c2fpdat register bit descriptions bit name function 7:0 c2fpdat c2 flash programming data register. this register is used to pass flash comm an ds, ad dresses, and data during c2 flash accesses. valid commands are listed below. 0x03: device erase 0x06: flash block read 0x07: flash block write 0x08: flash page erase
c8051f85x/86x 298 preliminary rev 0.6 d ocument c hange l ist revision 0.5 to revision 0.6 ? updated front page block diagram. ? updated adc supply current parameters in table 1.2, power consumption, on page 7. ? corrected flash programming voltage range in "table 1.4. flash memory" on page 10. ? added adc power-on time specification in table 1.7, adc, on page 12. ? added section "1.2. typical power curves" on page 17. ? corrected derivid information in "table 11.2. derivid register bit descriptions" on page 63. ? updated adc chapter ("14. analog-to-digital converter (adc0)" on page 78) and expanded section "14.5. power considerations" on p age 84 with recommended power configuration settings. ? updated figure 21.1, port i/o functional block diagram, on page 178. ? corrected reset value in register 24.5, smb0adm: smbus0 slave address mask, on page 250. ? corrected description of ie0 in "table 25.4. tcon register bit descriptions" on page 262.
c8051f85x/86x preliminary rev 0.6 299 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omer s d ifferentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories, silicon labs, and precisi on32 ar e trade marks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered tr ademarks of their respective holders the information in this document is believed to be accurate in a ll respects at the time of public ation but is subject to change without notice. silicon laboratories assumes no responsibi lity for errors and omissions , and disclaims responsibilit y for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its produ cts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or ci rcuit, and specifically discla ims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a situation where personal injury or death may occur. shoul d buyer purchase or use silicon laborator ies products for any such unintended or unaut horized application, buyer shall indemnify and hold silic on laboratories harmless against all claims and damages.

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